Abstract
A long channel backplane PCI Express (PCI-E) 8-Gbps transmission technology for next-generation high-speed I/O applications is adopted in a scale-out x86 CPU based server. Traditional Red river technology has the disadvantage of severe random jitter, crosstalk, power supply noise and high Bit Error Ratio. High speed signal simulation technology is applied here and Re-timer chip is selected for the long distance transmission of 8-Gbps PCI-E Gen3 signals. The signal transmission model is built, based on which the simulation tool is used to optimize design of connector via, cascade connection S parameter model of all sub-links and connectors. The whole S parameter model of PCI-E link is built, followed by which the PCB boards of the system are designed. CTLE and DFE parameters of Re-timer can be tuned to achieve desirable Bit Error Ratio and Contour Eye Diagram. The electrical properties of the whole PCI-E physical link are measured using High-Speed Digital Oscilloscope and BERT (Bit Error Ratio Tester) Scope. Prospective results are achieved and robustness of the server system is evaluated.
This work is supported by Sugon Program of Intelligent Manufacturing Standardization of Ministry of Industry and Information Technology (No. 2016ZXFB01001).
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Zhang, Y., Wang, L., Liu, J., Peng, Y., Pu, J., Sun, G. (2019). Evaluation and Testing of PCI Express 8-Gbps Re-timer in Storage Server. In: Sun, X., Pan, Z., Bertino, E. (eds) Artificial Intelligence and Security. ICAIS 2019. Lecture Notes in Computer Science(), vol 11634. Springer, Cham. https://doi.org/10.1007/978-3-030-24271-8_1
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DOI: https://doi.org/10.1007/978-3-030-24271-8_1
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