Skip to main content

On Compact Mappings for Multicore Systems

  • Conference paper
  • First Online:
Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2019)

Abstract

Application mapping is key for efficient multicore processing, i.e., selecting which resources to allocate to a given application, like computation to cores. Mapping is increasingly difficult in multi-application scenarios, where resource contention might degrade the performance of an application. In order to solve this, a promising avenue is to consider “compact” mappings, those which require a small and (geometrically) compact area within the chip. Compact mappings should decrease contention between applications by providing regional isolation and allowing multiple applications to be mapped simply. Previous work has shown that compact mappings can significantly outperform mappings obtained with a random strategy. In this paper we investigate the promise of compact mappings by running extensive simulations on Noxim, a cycle-accurate network-on-chip simulator. Results show the promises of compact mappings do not hold up in practice. When comparing to mappings selected with a heuristic better than simply choosing cores at random, our experiments do not indicate significant advantages from compact mappings. We outline possible reasons for this.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Balkind, J., et al.: OpenPiton: an open source manycore research framework. In: Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2016, pp. 217–232. ACM, New York (2016)

    Google Scholar 

  2. Castrillon, J., Leupers, R., Ascheid, G.: MAPS: mapping concurrent dataflow applications to heterogeneous MPSoCs. IEEE Trans. Industr. Inf. 9(1), 527–545 (2013)

    Article  Google Scholar 

  3. Castrillon, J., Tretter, A., Leupers, R., Ascheid, G.: Communication-aware mapping of KPN applications onto heterogeneous MPSoCs. In: DAC 2012: Proceedings of the 49th Annual Conference on Design Automation (2012)

    Google Scholar 

  4. Catania, V., Mineo, A., Monteleone, S., Palesi, M., Patti, D.: Cycle-accurate network on chip simulation with noxim. ACM Trans. Model. Comput. Simul. 27(1), 4:1–4:25 (2016)

    Article  Google Scholar 

  5. Eker, J., et al.: Taming heterogeneity-the ptolemy approach. Proc. IEEE 91(1), 127–144 (2003)

    Article  Google Scholar 

  6. Goens, A., Khasanov, R., Hähnel, M., Smejkal, T., Härtig, H., Castrillon, J.: Tetris: a multi-application run-time system for predictable execution of static mappings. In: Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems (SCOPES 2017), pp. 11–20. ACM, New York (2017)

    Google Scholar 

  7. Goens, A., Menard, C., Castrillon, J.: On the representation of mappings to multicores. In: Proceedings of the IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2018), pp. 184–191. Vietnam National University, Hanoi, September 2018

    Google Scholar 

  8. Hansson, A., Goossens, K., Bekooij, M., Huisken, J.: CoMPSoC: a template for composable and predictable multi-processor system on chips. ACM Trans. Des. Autom. Electron. Syst. (TODAES) 14(1), 2 (2009)

    Google Scholar 

  9. Kumar, A., Mesman, B., Theelen, B., Corporaal, H., Ha, Y.: Analyzing composability of applications on mpsoc platforms. J. Syst. Architect. 54(3), 369–383 (2008)

    Article  Google Scholar 

  10. Mellanox Technologies. TILE-Gx36 processor (2015). http://www.mellanox.com/related-docs/prod_multi_core/PB_TILE-Gx36.pdf. Accessed 22 May 2019

  11. Mellanox Technologies. TILE-Gx72 processor (2015). http://www.mellanox.com/related-docs/prod_multi_core/PB_TILE-Gx72.pdf. Accessed 22 May 2019

  12. Nikolov, H., et al.: Daedalus: toward composable multimedia mp-soc design. In: Proceedings of the 45th Annual Design Automation Conference, pp. 574–579. ACM (2008)

    Google Scholar 

  13. Pimentel, A.D., Erbas, C., Polstra, S.: A systematic approach to exploring embedded system architectures at multiple abstraction levels. IEEE Trans. Comput. 55(2), 99–112 (2006)

    Article  Google Scholar 

  14. Quan, W., Pimentel, A.D.: A hybrid task mapping algorithm for heterogeneous MPSoCs. ACM Trans. Embedded Comput. Syst. (TECS) 14(1), 14 (2015)

    Google Scholar 

  15. Singh, A.K., Shafique, M., Kumar, A., Henkel, J.: Mapping on multi/many-core systems: survey of current and emerging trends. In: Proceedings of the 50th Annual Design Automation Conference, p. 1. ACM (2013)

    Google Scholar 

  16. Sodani, A., et al.: Knights landing: second-generation intel xeon phi product. IEEE Micro 36(2), 34–46 (2016)

    Article  Google Scholar 

  17. Tam, S.M., et al.: Skylake-sp: a 14nm 28-core xeon® processor. In: 2018 IEEE International Solid - State Circuits Conference - (ISSCC), pp. 34–36, February 2018

    Google Scholar 

  18. Thiele, L., Bacivarov, I., Haid, W., Huang, K.: Mapping applications to tiled multiprocessor embedded systems. In: Seventh International Conference on Application of Concurrency to System Design, ACSD 2007, pp. 29–40. IEEE (2007)

    Google Scholar 

  19. Weichslgartner, A., Gangadharan, D., Wildermann, S., Glaß, M., Teich, J.: Daarm: design-time application analysis and run-time mapping for predictable execution in many-core systems. In: 2014 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ ISSS), pp. 1–10. IEEE (2014)

    Google Scholar 

  20. Weichslgartner, A., Wildermann, S., Götzfried, J., Freiling, F., Glaß, M., Teich, J.: Design-time/run-time mapping of security-critical applications in heterogeneous MPSoCs. In: Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, pp. 153–162. ACM (2016)

    Google Scholar 

  21. Yang, B., Guang, L., Xu, T.C., Säntti, T., Plosila, J.: Multi-application mapping algorithm for network-on-chip platforms. In: 2010 IEEE 26th Convention of Electrical and Electronics Engineers in Israel, p. 000540. IEEE (2010)

    Google Scholar 

Download references

Acknowledgments

This work was supported in part by the Center for Advancing Electronics Dresden (cfaed) and the Studienstiftung des deutschen Volkes.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Andrés Goens .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2019 Springer Nature Switzerland AG

About this paper

Check for updates. Verify currency and authenticity via CrossMark

Cite this paper

Goens, A., Menard, C., Castrillon, J. (2019). On Compact Mappings for Multicore Systems. In: Pnevmatikatos, D., Pelcat, M., Jung, M. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2019. Lecture Notes in Computer Science(), vol 11733. Springer, Cham. https://doi.org/10.1007/978-3-030-27562-4_23

Download citation

  • DOI: https://doi.org/10.1007/978-3-030-27562-4_23

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-27561-7

  • Online ISBN: 978-3-030-27562-4

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics