Abstract
The design of an FPGA hardware architecture requires, traditionally, its description in a dedicated language (Hardware Description Language, HDL), which is often not well suited to manage wide and complex models. The design process can be simplified if the entire architecture can be described in a high abstraction level framework such as Simulink. In this paper a Simulink model-based design of a pipelined accumulator suitable for applications such as Support Vector Machine algorithms is presented. The compatibility with the HDL Coder workflow enables the direct FPGA model implementation. Moreover, the workflow output has been compared with a native VHDL equivalent floating-point accumulator intellectual property.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Bassoli M, Bianchi V, De Munari I (2018) A plug and play IoT wi-fi smart home system for human monitoring. Electronics 7(9):200
Montalto F, Guerra C, Bianchi V, De Munari I, Ciampolini P (2015) MuSA: wearable multi sensor assistant for human activity recognition and indoor localization. Biosyst Biorobotics 11:81–92
Guerra C, Bianchi V, De Munari I, Ciampolini P (2015) CARDEAGate: low-cost, ZigBee-based localization and identification for AAL purposes. In: 2015 IEEE Instrumentation and Measurement Technology Conference (I2MTC)
Bianchi V, Bassoli M, Lombardo G, Fornacciari P, Mordonini M, De Munari I (2019) IoT wearable sensor and deep learning: an integrated approach for personalized human activity recognition in a smart home environment. IEEE Internet Things J 6(5):8553–8562
Gaikwad NB, Tiwari V, Keskar A, Shivaprakash NC (2019) Efficient FPGA implementation of multilayer perceptron for real-time human activity classification. IEEE Access 7(8651457):26696–26706
Giardino D, Matta M, Re M, Silvestri F, Spanò S (2018) IP generator tool for efficient hardware acceleration of self-organizing maps. In: International Conference on Applications in Electronics Pervading Industry, Environment and Society (APPLEPIES)
Hai JCT, Pun OC, Haw TW (2015) Accelerating video and image processing design for FPGA using HDL Coder and Simulink. In: 2015 IEEE Conference on Sustainable Utilization and Development in Engineering and Technology (CSUDET)
Michael T, Reynolds S, Woolford T (2018) Designing a generic, software-defined multimode radar simulator for FPGAs using Simulink® HDL Coder and Speedgoat real-time hardware. In: 2018 International Conference on Radar (RADAR)
Choe J et al (2019) Model-based design and DSP code generation using Simulink® for power electronics applications. In: 2019 10th International Conference on Power Electronics and ECCE Asia (ICPE 2019–ECCE Asia), pp 923–926
Perry S (2009) Model based design needs high level synthesis—a collection of high level synthesis techniques to improve productivity and quality of results for model based electronic design. In: 2009 Design, Automation and Test in Europe Conference and Exhibition (DATE ’09), pp 1202–1207
Flynn MJ, Oberman SF (2001) Advanced computer arithmetic design
Nagar KK, Bakos JD (2009) A high-performance double precision accumulator. In: 2009 International Conference on Field-Programmable Technology (FPT’09)
Ni LM, Hwang K (1985) Vector-reduction techniques for arithmetic pipelines. IEEE Trans Comput C–34(5):404–411
Sips HJ, Lin H (1991) An improved vector-reduction method. IEEE Trans Comput 40(2):214–217
Luo Z, Martonosi M (2000) Accelerating pipelined integer and floating-point accumulations in configurable hardware with delayed addition techniques. IEEE Trans Comput 49(3):208–218
Wang X, Braganza S, Leeser M (2006) Advanced components in the variable precision floating-point library. In: 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)
Zhuo L, Morris GR, Prasanna VK (2007) High-performance reduction circuits using deeply pipelined operators on FPGAs. IEEE Trans Parallel Distrib Syst 18(10):1377–1392
Zhuo L, Morris GR, Prasanna VK (2005) Designing scalable FPGA-based reduction circuits using pipelined floating-point cores. In: 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2005)
Tai Y-G, Lo C-TD, Psarris K (2012) Accelerating matrix operations with improved deeply pipelined vector reduction. IEEE Trans Parallel Distrib Syst 23(2):202–210
Huang M, Andrews D (2013) Modular design of fully pipelined reduction circuits on FPGAs. IEEE Trans Parallel Distrib Syst 24(9):1818–1826
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2020 Springer Nature Switzerland AG
About this paper
Cite this paper
Bassoli, M., Bianchi, V., De Munari, I. (2020). A Simulink Model-Based Design of a Floating-Point Pipelined Accumulator with HDL Coder Compatibility for FPGA Implementation. In: Saponara, S., De Gloria, A. (eds) Applications in Electronics Pervading Industry, Environment and Society. ApplePies 2019. Lecture Notes in Electrical Engineering, vol 627. Springer, Cham. https://doi.org/10.1007/978-3-030-37277-4_19
Download citation
DOI: https://doi.org/10.1007/978-3-030-37277-4_19
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-37276-7
Online ISBN: 978-3-030-37277-4
eBook Packages: Physics and AstronomyPhysics and Astronomy (R0)