Skip to main content
SpringerLink
Log in

Implementing On-Chip Wireless Communication in Multi-stage Interconnection NoCs

  • Conference paper
  • First Online:
Advanced Information Networking and Applications (AINA 2020)

Part of the book series: Advances in Intelligent Systems and Computing ((AISC,volume 1151))

Abstract

Current MultiProcessor System-on-Chips exploit the Network-on-Chip (NoC) design paradigm as a viable solution to get an efficient and scalable communication backbone. As the number of integrated cores keeps growing, alternatives to the multi-hop nature of NoCs like Wireless Networks-on-Chip (WiNoCs) have been proposed to provide a subset of network nodes with a wireless interface that enables long-range communications in a single hop. In this work, we propose the use of on-chip wireless communication on Multi-stage Interconnection Networks (MINs) based NoCs. After extending the well-known Noxim platform to support Wireless MINs architectures, we perform an extensive set of cycle-level estimation demonstrating that, while traditionally used in high-performance parallel computing, wireless-augmented MINs represent a very promising candidate for the applicability of on-chip radio communications technologies, with a noticeable improvement in both average delay and saturation point, at the cost of an estimated energy overhead ranging from \(2.8\%\) up to \(18.4\%\) in the case of 128 core nodes.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 169.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 219.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Abadal, S., Alarcón, E., Cabellos-Aparicio, A., Lemme, M.C., Nemirovsky, M.: Graphene-enabled wireless communication for massive multicore architectures. IEEE Commun. Mag. 51(11), 137–143 (2013)

    Article  Google Scholar 

  2. Abadal, S., Hosseininejad, S.E., Cabellos-Aparicio, A., Alarcón, E.: Graphene-based terahertz antennas for area-constrained applications. In: 2017 40th International Conference on Telecommunications and Signal Processing (TSP), pp. 817–820. IEEE, Piscataway (2017)

    Google Scholar 

  3. Agarwal, A., Iskander, C., Shankar, R.: Survey of network on chip (NoC) architectures & contributions. J. Eng. Comput. Architect. 3(1), 21–27 (2009)

    Google Scholar 

  4. Ansari, A.Q., Ansari, M.R., Khan, M.A.: Performance evaluation of various parameters of Network-on-Chip (NoC) for different topologies. In: 2015 Annual IEEE India Conference (INDICON), pp. 1–4. IEEE, Piscataway (2015)

    Google Scholar 

  5. Arjun, R.C., Mohan, M., Jossy, A., George, A., Sanju, V.: A fast and simple routing algorithm for butterfly architecture. In: 2016 IEEE International Conference on Advances in Computer Applications (ICACA), pp. 140–143. IEEE, Piscataway (2016). https://doi.org/10.1109/ICACA.2016.7887939

  6. Aydi, Y., Meftali, S., Dekeyser, J.L., Abid, M.: Design and performance evaluation of a reconfigurable delta MIN for MPSOC. In: 2007 International Conference on Microelectronics, pp. 115–118. IEEE, Piscataway (2007)

    Google Scholar 

  7. Banerjee, N., Vellanki, P., Chatha, K.S.: A power and performance model for network-on-chip architectures. In: Proceedings of the Conference on Design, Automation and Test in Europe, vol. 2, p. 21250. IEEE Computer Society, IEEE, Piscataway (2004)

    Google Scholar 

  8. Bhardwaj, V.P., Chauhan, P., et al.: On analysis and discussion of various performance parameters of omega and advance omega interconnection network. In: 2018 4th International Conference on Computing Communication and Automation (ICCCA), pp. 1–4. IEEE, Piscataway (2018)

    Google Scholar 

  9. Biberman, A., Preston, K., Hendry, G., Sherwood-Droz, N., Chan, J., Levy, J.S., Lipson, M., Bergman, K.: Photonic network-on-chip architectures using multilayer deposited silicon materials for high-performance chip multiprocessors. ACM J. Emerg. Technol. Comput. Syst. (JETC) 7(2), 7 (2011)

    Google Scholar 

  10. Bononi, L., Concer, N.: Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh. In: Proceedings of the Conference on Design, Automation and Test in Europe: Designers’ Forum, pp. 154–159. European Design and Automation Association, ACM, New York (2006)

    Google Scholar 

  11. Catania, V., Mineo, A., Monteleone, S., Palesi, M., Patti, D.: Cycle-accurate network on chip simulation with Noxim. ACM Trans. Model. Comput. Simul. (TOMACS) 27(1), 4:1–4:25 (2016)

    Article  Google Scholar 

  12. Catania, V., Mineo, A., Monteleone, S., Palesi, M., Patti, D.: Energy efficient transceiver in wireless network on chip architectures. In: Proceedings of the 2016 Conference on Design, Automation & Test in Europe, pp. 1321–1326. EDA Consortium, ACM, New York (2016)

    Google Scholar 

  13. Catania, V., Mineo, A., Monteleone, S., Palesi, M., Patti, D.: Improving energy efficiency in wireless network-on-chip architectures. ACM J. Emerg. Technol. Comput. Syst. (JETC) 14(1), 9 (2018)

    Google Scholar 

  14. Chang, K., Deb, S., Ganguly, A., Yu, X., Sah, S.P., Pande, P.P., Belzer, B., Heo, D.: Performance evaluation and design trade-offs for wireless network-on-chip architectures. ACM J. Emerg. Technol. Comput. Syst. (JETC) 8(3), 23 (2012)

    Google Scholar 

  15. Chen, J., Li, C., Gillard, P.: Network-on-Chip (NoC) topologies and performance: a review. In: Proceedings of the 2011 Newfoundland Electrical and Computer Engineering Conference (NECEC), pp. 1–6 (2011)

    Google Scholar 

  16. Dinh, V.N., Ho, M.V., Nguyen, V.C., Ngo, T.S., Charles, E.: The analyzes of network-on-chip architectures based on Noxim simulator. In: International Conference on Advances in Information and Communication Technology, pp. 603–611. Springer, Dordrecht (2016)

    Google Scholar 

  17. Hammami, O., M’zah, A., Hamwi, K.: Design of 3D-IC for butterfly NOC based 64 PE-multicore: analysis and design space exploration. In: 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International, pp. 1–4. IEEE, Piscataway (2011)

    Google Scholar 

  18. Hammami, O., M’zah, A., Jabbar, M., Houzet, D.: 3D IC implementation for MPSOC architectures: mesh and butterfly based NoC. In: 2012 4th Asia Symposium on Quality Electronic Design (ASQED), pp. 155–159. IEEE, Piscataway (2012)

    Google Scholar 

  19. He, R., Delgado-Frias, J.G.: Fault tolerant interleaved switching fabrics for scalable high-performance routers. IEEE Trans. Parallel Distrib. Syst. 18(12), 1727–1739 (2007). https://doi.org/10.1109/TPDS.2007.1109

    Article  Google Scholar 

  20. Kim, R.G., Choi, W., Chen, Z., Pande, P.P., Marculescu, D., Marculescu, R.: Wireless NoC and dynamic VFI codesign: energy efficiency without performance penalty. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 24(7), 2488–2501 (2016)

    Article  Google Scholar 

  21. Lee, S.B., Tam, S.W., Pefkianakis, I., Lu, S., Chang, M.F., Guo, C., Reinman, G., Peng, C., Naik, M., Zhang, L., et al.: A scalable micro wireless interconnect structure for CMPs. In: Proceedings of the 15th Annual International Conference on Mobile Computing and Networking, pp. 217–228. ACM (2009)

    Google Scholar 

  22. Mohapatra, P.: Wormhole routing techniques for directly connected multicomputer systems. ACM Comput. Surv. 30(8), 374–410 (1998)

    Article  Google Scholar 

  23. Murray, J., Kim, R., Wettin, P., Pande, P.P., Shirazi, B.: Performance evaluation of congestion-aware routing with DVFs on a millimeter-wave small world wireless NoC. ACM J. Emerg. Technol. Comput. Syst. (JETC) 11(2), 1–22 (2014)

    Article  Google Scholar 

  24. Ogras, U.Y., Bogdan, P., Marculescu, R.: An analytical approach for network-on-chip performance analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(12), 2001–2013 (2010)

    Article  Google Scholar 

  25. Palesi, M., Collotta, M., Mineo, A., Catania, V.: An efficient radio access control mechanism for wireless network-on-chip architectures. J. Low Power Electron. Appl. 5(2), 38–56 (2015)

    Article  Google Scholar 

  26. Palesi, M., Patti, D., Fazzino, F., Monteleone, S.: Github - Noxim - the NoC simulator (2019). https://github.com/davidepatti/noxim

  27. Pande, P.P., Grecu, C., Jones, M., Ivanov, A., Saleh, R.: Performance evaluation and design trade-offs for network-on-chip interconnect architectures. IEEE Trans. Comput. 54(8), 1025–1040 (2005)

    Article  Google Scholar 

  28. Pande, P.P., Kim, R.G., Choi, W., Chen, Z., Marculescu, D., Marculescu, R.: The (low) power of less wiring: enabling energy efficiency in many-core platforms through wireless NoC. In: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 165–169. IEEE, Piscataway (2015)

    Google Scholar 

  29. Pavlidis, V.F., Friedman, E.G.: 3-D topologies for networks-on-chip. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 15(10), 1081–1090 (2007)

    Article  Google Scholar 

  30. Shacham, A., Bergman, K., Carloni, L.P.: Photonic networks-on-chip for future generations of chip multiprocessors. IEEE Trans. Comput. 57(9), 1246–1260 (2008). https://doi.org/10.1109/TC.2008.78

    Article  MathSciNet  Google Scholar 

  31. Swaminathan, K., Thakyal, D., Nambiar, S.G., Lakshminarayanan, G., Ko, S.B.: Enhanced Noxim simulator for performance evaluation of network on chip topologies. In: 2014 Recent Advances in Engineering and Computational Sciences (RAECS), pp. 1–5. IEEE, Piscataway (2014)

    Google Scholar 

  32. Vien, Q.T., Agyeman, M.O., Le, T.A., Mak, T.: On the nanocommunications at THz band in graphene-enabled wireless network-on-chip. Math. Prob. Eng. 2017, 1–13 (2017)

    Article  Google Scholar 

  33. Wang, C., Hu, W.H., Bagherzadeh, N.: A wireless network-on-chip design for multicore platforms. In: 2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing, pp. 409–416. IEEE (2011)

    Google Scholar 

  34. Wu, R., Wang, Y., Zhao, D.: A low-cost deadlock-free design of minimal-table rerouted XY-routing for irregular wireless NoCs. In: 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip, pp. 199–206. IEEE (2010)

    Google Scholar 

  35. Yang, L., Liu, W., Jiang, W., Li, M., Yi, J., Sha, E.H.M.: Application mapping and scheduling for network-on-chip-based multiprocessor system-on-chip with fine-grain communication optimization. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 24(10), 3027–3040 (2016)

    Article  Google Scholar 

  36. Zhang, J., Chen, Y., Xiao, R., Ling, X.: A cellular NoC architecture based on butterfly network coding (CBNOC). In: 2017 IEEE 17th International Conference on Communication Technology (ICCT), pp. 460–464. IEEE, Piscataway (2017). https://doi.org/10.1109/ICCT.2017.8359680

  37. Zhao, D., Wang, Y.: SD-MAC: design and synthesis of a hardware-efficient collision-free QoS-aware MAC protocol for wireless network-on-chip. IEEE Trans. Comput. 57(9), 1230–1245 (2008)

    Article  MathSciNet  Google Scholar 

  38. Zhao, D., Wang, Y., Li, J., Kikkawa, T.: Design of multi-channel wireless NoC to improve on-chip communication capacity! In: Proceedings of the Fifth ACM/IEEE International Symposium, pp. 177–184. IEEE (2011)

    Google Scholar 

Download references

Acknowledgement

This work was partially supported by the Institute of Advanced Studies of the University of Cergy-Pontoise under the Paris Seine Initiative for Excellence (“Investissements d’Avenir” ANR-16-IDEX-0008).

Author information

Authors and Affiliations

  1. CES Laboratory, National Engineering School of Sfax, Sfax, Tunisia

    Sirine Mnejja, Yassine Aydi & Mohamed Abid

  2. Institute of Advanced Studies & ETIS (UMR 8051 CNRS), University of Cergy-Pontoise, Cergy, France

    Salvatore Monteleone

  3. Department of Electrical, Electronic, and Computer Engineering, University of Catania, Catania, Italy

    Maurizio Palesi & Davide Patti

Authors
  1. Sirine Mnejja
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Yassine Aydi
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Mohamed Abid
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Salvatore Monteleone
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Maurizio Palesi
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. Davide Patti
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Davide Patti .

Editor information

Editors and Affiliations

  1. Department of Information and Communication Engineering, Faculty of Information Engineering, Fukuoka Institute of Technology, Fukuoka, Japan

    Leonard Barolli

  2. Department of Electrical Engineering and Information Technology, University of Naples “Frederico II”, Naples, Italy

    Flora Amato

  3. Department of Political Science, University of Campania “Luigi Vanvitelli”, Caserta, Italy

    Francesco Moscato

  4. Faculty of Business Administration, Rissho University, Tokyo, Japan

    Tomoya Enokido

  5. Department of Advanced Sciences, Faculty of Science and Engineering, Hosei University, Tokyo, Japan

    Makoto Takizawa

Rights and permissions

Reprints and permissions

Copyright information

© 2020 Springer Nature Switzerland AG

About this paper

Check for updates. Verify currency and authenticity via CrossMark

Cite this paper

Mnejja, S., Aydi, Y., Abid, M., Monteleone, S., Palesi, M., Patti, D. (2020). Implementing On-Chip Wireless Communication in Multi-stage Interconnection NoCs. In: Barolli, L., Amato, F., Moscato, F., Enokido, T., Takizawa, M. (eds) Advanced Information Networking and Applications. AINA 2020. Advances in Intelligent Systems and Computing, vol 1151. Springer, Cham. https://doi.org/10.1007/978-3-030-44041-1_48

Download citation

Publish with us

Policies and ethics

Search

Navigation