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CTA: A Critical Task Aware Scheduling Mechanism for Dataflow Architecture

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Algorithms and Architectures for Parallel Processing (ICA3PP 2020)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 12452))

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Abstract

Critical tasks directly affect the overall performance of a program, especially in dataflow architecture. The reason is that dependency between tasks in dataflow scenarios is much more complex than those in control-flow scenarios. However, previous works fail to sufficiently accelerate the critical task because most of them only applied optimization for static critical tasks, without considering the runtime status during execution. We propose a critical task aware (CTA) scheduling mechanism for dataflow architecture. By adopting co-optimization of hardware and software, higher execution priorities are assigned to the critical tasks for better scheduling. The experimental results show that our mechanism increases the computational performance by 14%–78%, and increases the power efficiency by 11%–41%.

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References

  1. Akbari, O., Kamal, M., Afzali-Kusha, A., Pedram, M., Shafique, M.: PX-CGRA: polymorphic approximate coarse-grained reconfigurable architecture. In: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 413–418. IEEE (2018)

    Google Scholar 

  2. Chen, Y.H., Krishna, T., Emer, J.S., Sze, V.: Eyeriss: an energy-efficient reconfigurable accelerator for deep convolutional neural networks. IEEE J. Solid-State Circ. 52(1), 127–138 (2016)

    Article  Google Scholar 

  3. Chen, Y.H., Yang, T.J., Emer, J., Sze, V.: Eyeriss v2: a flexible accelerator for emerging deep neural networks on mobile devices. IEEE J. Emerg. Sel. Top. Circ. Syst. 9(2), 292–308 (2019)

    Article  Google Scholar 

  4. Coons, K.E., Chen, X., Burger, D., McKinley, K.S., Kushwaha, S.K.: A spatial path scheduling algorithm for edge architectures. ACM SIGOPS Oper. Syst. Rev. 40(5), 129–140 (2006)

    Article  Google Scholar 

  5. Dennis, J.B.: First version of a data flow procedure language. In: Robinet, B. (ed.) Programming Symposium. LNCS, vol. 19, pp. 362–376. Springer, Heidelberg (1974). https://doi.org/10.1007/3-540-06859-7_145

    Chapter  Google Scholar 

  6. Fan, D., et al.: SmarCO: an efficient many-core processor for high-throughput applications in datacenters. In: 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 596–607. IEEE (2018)

    Google Scholar 

  7. Fu, H., et al.: Scaling reverse time migration performance through reconfigurable dataflow engines. IEEE Micro 34(1), 30–40 (2013)

    Article  Google Scholar 

  8. Hiraki, K., Sekiguchi, S., Shimada, T.: Efficient vector processing on a dataflow supercomputer sigma-1. In: Supercomputing 1988: Proceedings of the 1988 ACM/IEEE Conference on Supercomputing, vol. I, pp. 374–381. IEEE (1988)

    Google Scholar 

  9. Hoffmann, H.: Stream algorithms and architecture. Ph.D. thesis, Massachusetts Institute of Technology (2003)

    Google Scholar 

  10. Jouppi, N.P., et al.: In-datacenter performance analysis of a tensor processing unit. In: Proceedings of the 44th Annual International Symposium on Computer Architecture, pp. 1–12 (2017)

    Google Scholar 

  11. Krizhevsky, A., Sutskever, I., Hinton, G.E.: ImageNet classification with deep convolutional neural networks. In: Advances in Neural Information Processing Systems, pp. 1097–1105 (2012)

    Google Scholar 

  12. Kyriacou, C., Evripidou, P., Trancoso, P.: Data-driven multithreading using conventional microprocessors. IEEE Trans. Parallel Distrib. Syst. 17(10), 1176–1188 (2006)

    Article  Google Scholar 

  13. Lattner, C., Adve, V.: LLVM: a compilation framework for lifelong program analysis & transformation. In: International Symposium on Code Generation and Optimization, CGO 2004, pp. 75–86. IEEE (2004)

    Google Scholar 

  14. Long, J., Shelhamer, E., Darrell, T.: Fully convolutional networks for semantic segmentation. In: Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, pp. 3431–3440 (2015)

    Google Scholar 

  15. Nagarajan, R., Kushwaha, S.K., Burger, D., McKinley, K.S., Lin, C., Keckler, S.W.: Static placement, dynamic issue (SPDI) scheduling for edge architectures. In: Proceedings. 13th International Conference on Parallel Architecture and Compilation Techniques, PACT 2004, pp. 74–84. IEEE (2004)

    Google Scholar 

  16. Oriato, D., Tilbury, S., Marrocu, M., Pusceddu, G.: Acceleration of a meteorological limited area model with dataflow engines. In: 2012 Symposium on Application Accelerators in High Performance Computing, pp. 129–132. IEEE (2012)

    Google Scholar 

  17. Oskin, M.H., Swanson, S.J., Eggers, S.J.: Wavescalar architecture having a wave order memory, uS Patent 7,657,882, 2 February 2010

    Google Scholar 

  18. Pratas, F., Oriato, D., Pell, O., Mata, R.A., Sousa, L.: Accelerating the computation of induced dipoles for molecular mechanics with dataflow engines. In: 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines, pp. 177–180. IEEE (2013)

    Google Scholar 

  19. Rahman, M., Venugopal, S., Buyya, R.: A dynamic critical path algorithm for scheduling scientific workflow applications on global grids. In: Third IEEE International Conference on e-Science and Grid Computing (e-Science 2007), pp. 35–42. IEEE (2007)

    Google Scholar 

  20. Sankaralingam, K., et al.: Exploiting ILP, TLP, and DLP with the polymorphous trips architecture. In: Proceedings of the 30th Annual International Symposium on Computer Architecture, pp. 422–433. IEEE (2003)

    Google Scholar 

  21. Schulz, M.: Extracting critical path graphs from MPI applications. In: 2005 IEEE International Conference on Cluster Computing, pp. 1–10. IEEE (2005)

    Google Scholar 

  22. Son, J.H., Kim, J.S., Kim, M.H.: Extracting the workflow critical path from the extended well-formed workflow schema. J. Comput. Syst. Sci. 70(1), 86–106 (2005)

    Article  MathSciNet  Google Scholar 

  23. Son, J.H., Kim, M.H.: Analyzing the critical path for the well-formed workflow schema. In: Proceedings Seventh International Conference on Database Systems for Advanced Applications, DASFAA 2001, pp. 146–147. IEEE (2001)

    Google Scholar 

  24. Swanson, S., Michelson, K., Schwerin, A., Oskin, M.: WaveScalar. In: Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-36, pp. 291–302. IEEE (2003)

    Google Scholar 

  25. Tan, X., et al.: A pipelining loop optimization method for dataflow architecture. J. Comput. Sci. Technol. 33(1), 116–130 (2018)

    Article  MathSciNet  Google Scholar 

  26. Tian, Y., Gu, Y., Ekici, E., Ozguner, F.: Dynamic critical-path task mapping and scheduling for collaborative in-network processing in multi-hop wireless sensor networks. In: 2006 International Conference on Parallel Processing Workshops (ICPPW 2006), pp. 8-pp. IEEE (2006)

    Google Scholar 

  27. Voitsechov, D., Etsion, Y.: Single-graph multiple flows: energy efficient design alternative for GPGPUs. ACM SIGARCH Comput. Archit. News 42(3), 205–216 (2014)

    Article  Google Scholar 

  28. Ye, X., Fan, D., Sun, N., Tang, S., Zhang, M., Zhang, H.: SimICT: a fast and flexible framework for performance and power evaluation of large-scale architecture. In: International Symposium on Low Power Electronics and Design (ISLPED), pp. 273–278. IEEE (2013)

    Google Scholar 

  29. Ye, X., et al.: An efficient dataflow accelerator for scientific applications. Future Gener. Comput. Syst. 112, 580–588 (2020)

    Article  Google Scholar 

  30. Ye, X., et al.: Applying CNN on a scientific application accelerator based on dataflow architecture. CCF Trans. High Perform. Comput. 1(3–4), 177–195 (2019)

    Article  Google Scholar 

Download references

Acknowledgment

This work was supported by the project of the state grid corporation of China in 2020 “Integration technology research and prototype development for high end controller chip” under Grant No. 5700-202041264A-0-0-00.

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Authors and Affiliations

  1. State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, 100190, China

    Yan Ou, Yujing Feng, Xinxin Wu, Wenming Li, Xiaochun Ye & Dongrui Fan

  2. School of Computer and Control Engineering, University of Chinese Academy of Sciences, Beijing, 100049, China

    Yan Ou, Xinxin Wu & Dongrui Fan

  3. Beijing Smartchip Microelectronics Technology Company Limited, Haidian District, Beijing, 100000, China

    Chongfei Shen

  4. State Key Laboratory of Mathematical Engineering and Advanced Computing, Wuxi, 214125, Jiangsu, China

    Xiaochun Ye

Authors
  1. Yan Ou
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  2. Chongfei Shen
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  3. Yujing Feng
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  4. Xinxin Wu
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  5. Wenming Li
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  6. Xiaochun Ye
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  7. Dongrui Fan
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Corresponding author

Correspondence to Dongrui Fan .

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Editors and Affiliations

  1. Columbia University, New York, NY, USA

    Meikang Qiu

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Ou, Y. et al. (2020). CTA: A Critical Task Aware Scheduling Mechanism for Dataflow Architecture. In: Qiu, M. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2020. Lecture Notes in Computer Science(), vol 12452. Springer, Cham. https://doi.org/10.1007/978-3-030-60245-1_5

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