Abstract
The complexity and outsourcing trend of modern System-on-Chips (SoC) has made Hardware Trojan (HT) a real threat for the SoC security. In the state-of-the-art, many techniques have been proposed in order to detect the HT insertion. Side-channel based methods emerge as a good approach used for the HT detection. They can extract any difference in the power consumption, electromagnetic (EM) emanation, delay propagation, etc. caused by the HT insertion/modification in the genuine design. Therefore, they can be applied to detect the HT even when it is not activated. However, these methods are evaluated on overly simple design prototypes such as AES coprocessors. Moreover, the analytical approach used for these methods is limited by some statistical metrics such as the direct comparison of EM traces or the T-test coefficients. In this paper, we propose two new detection methodologies based on Machine Learning algorithms. The first method consists in applying the supervised Machine Learning (ML) algorithms on raw EM traces for the classification and detection of HT. It offers a detection rate close to 90% and false negative smaller than 5%. For the second method, we propose a method based on the Outlier/Novelty algorithms. This method combined with the T-test based signal processing technique, when compared with state-of-the-art, offers a better performance with a detection rate close to 100% and a false positive smaller than 1%. We have evaluated the performance of our method on a complex target design: RISC-V generic processors. The three HTs with the corresponding sizes of 0.53%, 0.27% and 0.1% of the RISC-V processors are inserted for the experimentation. The experimental results show that the inserted HTs, though minimalist, can be detected using our new methodology.
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References
Balasch, J., Gierlichs, B., Verbauwhede, I.: Electromagnetic circuit fingerprints for hardware trojan detection. In: 2015 IEEE International Symposium on Electromagnetic Compatibility (EMC), pp. 246–251, August 2015
Banga, M., Hsiao, M.S.: A novel sustained vector technique for the detection of hardware trojans. In: International Conference on VLSI Design, pp. 327–332. IEEE (2009)
Banga, M., Hsiao, M.S.: ODETTE : a non-scan design-for-test methodology for trojan detection in ICs. In: International Workshop on Hardware-Oriented Security and Trust (HOST), pp. 18–23. IEEE (2011)
Bounsiar, A., Madden, M.G.: One-class support vector machines revisited. In: 2014 International Conference on Information Science Applications (ICISA), pp. 1–4, May 2014
Chiu, A.L.M., Fu, A.W.C.: Enhancements on local outlier detection. In: Seventh International Database Engineering and Applications Symposium, Proceedings 2003, pp. 298–307, July 2003
Courbon, F., Loubet-Moundi, P., Fournier, J.J., Tria, A.: A high efficiency hardware trojan detection technique based on fast SEM imaging. In: Nebel, W., Atienza, D. (eds.) Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, 9–13 March 2015, pp. 788–793. ACM, Grenoble (2015)
Ding, A.A., Chen, C., Eisenbarth, T.: Simpler, faster, and more robust T-test based leakage detection. In: Standaert, F.-X., Oswald, E. (eds.) COSADE 2016. LNCS, vol. 9689, pp. 163–183. Springer, Cham (2016). https://doi.org/10.1007/978-3-319-43283-0_10
He, J., Zhao, Y., Guo, X., Jin, Y.: Hardware trojan detection through chip-free electromagnetic side-channel statistical analysis. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(10), 2939–2948 (2017)
Hearst, M.A., Dumais, S.T., Osuna, E., Platt, J., Scholkopf, B.: Support vector machines. IEEE Intell. Syst. Appl. 13(4), 18–28 (1998)
Jha, S., Jha, S.K.: Randomization based probabilistic approach to detect trojan circuits. In: Proceedings of the 2008 11th IEEE High Assurance Systems Engineering Symposium, HASE 2008, pp. 117–124. IEEE Computer Society (2008)
Jin, Y., Kupp, N., Makris, Y.: Experiences in hardware trojan design and implementation. In: Proceedings of the 2009 IEEE International Workshop on Hardware-Oriented Security and Trust, HOST 2009, pp. 50–57. IEEE Computer Society, Washington, DC (2009)
King, S.T., Tucek, J., Cozzie, A., Grier, C., Jiang, W., Zhou, Y.: Designing and implementing malicious hardware. In: Proceedings of the 1st Usenix Workshop on Large-Scale Exploits and Emergent Threats, LEET 2008, pp. 5:1–5:8. USENIX Association, Berkeley (2008)
Lecomte, M., Fournier, J., Maurine, P.: An on-chip technique to detect hardware trojans and assist counterfeit identification. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(12), 3317–3330 (2017)
Liu, F.T., Ting, K.M., Zhou, Z.H.: Isolation forest. In: 2008 Eighth IEEE International Conference on Data Mining, pp. 413–422, December 2008
Liu, Y., Jin, Y., Nosratinia, A., Makris, Y.: Silicon demonstration of hardware trojan design and detection in wireless cryptographic ICs. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(4), 1506–1519 (2017)
Muehlberghuber, M., Gürkaynak, F.K., Korak, T., Dunst, P., Hutter, M.: Red team vs. blue team hardware trojan analysis: detection of a hardware trojan on an actual ASIC. In: 2nd International Workshop on Hardware and Architectural Support for Security and Privacy (HASP 2013), pp. 1:1–1:8. ACM, New York(2013). http://dx.doi.org/10.1145/2487726.2487727
Ngo, X.T., Danger, J.L., Guilley, S., Najm, Z., Emery, O.: Hardware property checker for run-time hardware trojan detection. In: 2015 European Conference on Circuit Theory and Design (ECCTD), pp. 1–4, August 2015
Rad, R., Plusquellic, J., Tehranipoor, M.: Sensitivity analysis to hardware trojans using power supply transient signals. In: Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust, HST 2008, pp. 3–7. IEEE Computer Society, Washington, DC (2008)
SiFive: Source files for SiFive’s Freedom platforms, 29 November 2016. https://github.com/sifive/freedom
Skorobogatov, S., Woods, C.: Breakthrough silicon scanning discovers backdoor in military chip. In: Prouff, E., Schaumont, P. (eds.) CHES 2012. LNCS, vol. 7428, pp. 23–40. Springer, Heidelberg (2012). https://doi.org/10.1007/978-3-642-33027-8_2
Söll, O., Korak, T., Muehlberghuber, M., Hutter, M.: EM-based detection of hardware trojans on FPGAs. In: 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), pp. 84–87, May 2014
Torrance, R., James, D.: The state-of-the-art in IC reverse engineering. In: Clavier, C., Gaj, K. (eds.) CHES 2009. LNCS, vol. 5747, pp. 363–381. Springer, Heidelberg (2009). https://doi.org/10.1007/978-3-642-04138-9_26
Wolf, C.: PicoRV32 - A Size-Optimized RISC-V CPU. https://github.com/cliffordwolf/picorv32
Worley, K., Rahman, M.T.: Supervised machine learning techniques for trojan detection with ring oscillator network. In: 2019 SoutheastCon, pp. 1–7, April 2019
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Takahashi, J. et al. (2020). Machine Learning Based Hardware Trojan Detection Using Electromagnetic Emanation. In: Meng, W., Gollmann, D., Jensen, C.D., Zhou, J. (eds) Information and Communications Security. ICICS 2020. Lecture Notes in Computer Science(), vol 12282. Springer, Cham. https://doi.org/10.1007/978-3-030-61078-4_1
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