Abstract
Superscalar microarchitectures include register renaming units where architectural registers are renamed to physical registers. Modern renaming units are required to rename more than one instruction per clock cycle. Conventional renaming units use parallel circuits to simultaneously rename more than one instruction. We propose a serial circuit to rename more than one instruction in sequential manner. Then we propose a pipelined implementation of the serial renaming unit. We compare the proposed (pipelined) serial register renaming unit with the ordinary register renaming unit.
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References
Hennessy, J.L., Patterson, D.A.: Computer Architecture: A Quantitative Approach, 5th edn. Elsevier, Netherlands (2011)
Smith, J.E., Sohi, G.S.: The microarchitecture of superscalar processors. Proc. IEEE 83(12), 1609–1624 (1995)
Kessler, R.: The Alpha 21264 microprocessor. IEEE Micro 19(2), 24–36 (1999)
Buti, T.N., et al.: Organization and implementation of the register-renaming mapper for out-of-order IBM POWER4 processors. IBM J. Res. Dev. 49(1), 167–188 (2005)
Tomasulo, R.M.: An efficient algorithm for exploiting multiple arithmetic units. IBM J. Res. Dev. 11(1), 25–33 (1967)
Hinton, G., et. al.: The microarchitecture of the Pentium® 4 processor. Intel Technol. J. (2001)
Sadasivam, S.K., Thompto, B.W., Kalla, R., Starke, W.J.: IBM Power9 processor architecture. IEEE Micro 37(2), 40–51 (2017)
Safi, E., Moshovos, A., Veneris, A.: Two-stage, pipelined register renaming. IEEE Trans. Very Large-Scale Integr. (VLSI) Syst. 19(10), 1926–1931 (2011)
Moshovos, A.: Power-aware register renaming. Technical report, Computer Engineering Group, University of Toronto (2002)
Kucuk, G., Ergin, O., Ponomarev, D., Ghose, K.: Reducing power dissipation of register alias tables in high-performance processors. IEE Proc. Comput. Digit. Tech. 152(6), 739–746 (2005)
Petit, S., Ubal, R., Sahuquillo, J., López, P.: Efficient register renaming and recovery for high-performance processors. IEEE Trans. Very Large-Scale Integr. (VLSI) Syst. 22(7), 1506–1514 (2014)
Vajapeyam, S., Mitra, T.: Improving superscalar instruction dispatch and issue by exploiting dynamic code sequences. ACM SIGARCH Comput. Archit. News 25(2), 1–12 (1997)
Shioya, R., Ando, H.: Energy efficiency improvement of renamed trace cache through the reduction of dependent path length. In: Proceedings of the IEEE 32nd International Conference on Computer Design (ICCD), New York, NY, USA, pp. 416–423. IEEE (2014)
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Spasov, D. (2020). Pipelined Serial Register Renaming. In: Dimitrova, V., Dimitrovski, I. (eds) ICT Innovations 2020. Machine Learning and Applications. ICT Innovations 2020. Communications in Computer and Information Science, vol 1316. Springer, Cham. https://doi.org/10.1007/978-3-030-62098-1_13
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DOI: https://doi.org/10.1007/978-3-030-62098-1_13
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