Skip to main content

Design and Analysis of RF/High-Speed SERDES in 28 nm CMOS Technology for Aerospace Applications

  • Conference paper
  • First Online:
Applications in Electronics Pervading Industry, Environment and Society (ApplePies 2020)

Abstract

This paper proposes a transistor-level design of a high-speed 10-bit Serializer-Deserializer (SerDes) circuit for Aerospace applications, in a 28 nm CMOS technology. A data-rate above 10 Gbit/s has been taken as a target for the development, together with a −50 °C to 125 °C temperature range. The extreme performance requirements made necessary the realization of a full-custom design and the use of Current Mode Logic (CML) circuits. This solution brings advantages in devices where high speeds are required, overcoming standard CMOS logic capabilities. Moreover, an aerospace application involves an analysis over radiation and their effect on integrated circuits. The relatively low presence of cumulative radiation doses in this environment let them to be neglected and to focus the attention on the disturbs coming from high-energy particles hitting the substrate (Single Event Effects). These, in fact, constitute one of the main causes of failures in electronic devices for avionic systems.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 169.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 219.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 219.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. https://www.esa.int/Enabling_Support/Space_Engineering_Technology/Onboard_Data_Processing/SpaceFibre

  2. Ciordia, Ó., Pérez, R., Pardo, C.: Optical communications for next generation automotive networks. In: 2017 22nd Microoptics Conference (MOC), Tokyo, pp. 24–25 (2017)

    Google Scholar 

  3. Saponara, S., Ciarpi, G., Groza, V.Z.: Design and experimental measurement of EMI reduction techniques for integrated switching DC/DC converters. Can. J. Electr. Comput. Eng. 40(2), 116–127 (2017)

    Google Scholar 

  4. https://auto-serdes.org/

  5. Ciarpi, G., Magazzù, G., Palla, F., Saponara, S.: Design, implementation, and experimental verification of 5 Gbps, 800 Mrad TID and SEU-tolerant optical modulators drivers. IEEE Trans. Circuits Syst. I Regul. Pap. 67(3), 829–838 (2020)

    Google Scholar 

  6. Ozsema, H.G., Kostak, D.: Full swing 20 GHz frequency divider with 1 V supply voltage in FD-SOI 28 nm technology. Microelectronic Systems Laboratory (LSM) Ecole Polytechnique Federale de Lausanne (EPFL), Lausanne (2010)

    Google Scholar 

  7. Szilagyi, L., Belfiore, G.: Low power inductor-less CML latch and frequency divider for full-rate 20 Gbps in 28-nm CMOS. Dresden University of Technology Chair for Circuit Design and Network Theory, Dresden (2013)

    Google Scholar 

  8. Heydari, P., Mohanavelu, R.: Design of Ultrahigh-Speed Low-Voltage CMOS CML Buffers and Latches. IEEE Trans. Very Large-Scale Integr. (VLSI) Syst. 12(10), 1081–1093 (2004)

    Google Scholar 

  9. Voinigescu, S.: High-Frequency Integrated Circuits. University of Toronto (2013)

    Google Scholar 

  10. DasGupta, S.: Trends in single event pulse widths and pulse shapes in deep submicron CMOS. Master of Science in Electrical Engineering, Nashville (2007)

    Google Scholar 

  11. Frontini, L.: Design of CMOS logic gates tolerant of single-event effects for extreme radiation environments. Università degli Studi di Milano, Dipartimento di Scienze Matematiche, Fisiche e Naturali (2014)

    Google Scholar 

  12. Black, J.D., et al.: HBD layout isolation techniques for multiple node charge collection mitigation. IEEE Trans. Nuclear Sci. 52(6), 2536–2541 (2005)

    Google Scholar 

  13. Agrawal, F.W.: Single event upset: an embedded tutorial. In: 21st International Conference on VLSI Design, Department of Electrical and Computer Engineering, Auburn University, Auburn, AL, 36849, USA (2008)

    Google Scholar 

  14. Nga, N.T.H., Lee, M.H., et al.: 10 Gb/s SerDes for bidirectional chip-to-memory optical interconnection. In: 2007 Conference on Lasers and Electro-Optics-Pacific Rim, pp. 1–2 (2007)

    Google Scholar 

  15. Cosimi, F.: Analysis and Design of RF/High-speed SERDES in 28nm CMOS technology for Aerospace Applications. Università di Pisa, Ingegneria dell’Informazione (2020)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding authors

Correspondence to Francesco Cosimi , Gabriele Ciarpi or Sergio Saponara .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2021 The Author(s), under exclusive license to Springer Nature Switzerland AG

About this paper

Check for updates. Verify currency and authenticity via CrossMark

Cite this paper

Cosimi, F., Ciarpi, G., Saponara, S. (2021). Design and Analysis of RF/High-Speed SERDES in 28 nm CMOS Technology for Aerospace Applications. In: Saponara, S., De Gloria, A. (eds) Applications in Electronics Pervading Industry, Environment and Society. ApplePies 2020. Lecture Notes in Electrical Engineering, vol 738. Springer, Cham. https://doi.org/10.1007/978-3-030-66729-0_21

Download citation

  • DOI: https://doi.org/10.1007/978-3-030-66729-0_21

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-66728-3

  • Online ISBN: 978-3-030-66729-0

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics