Abstract
Ad Hoc network is a new networking technology that does not rely on preset communication facilities, and is one of the important components of the next generation wireless communication network system. The OLSR (Optimized Link State Routing) protocol is a classic proactive routing protocol in Ad Hoc networks. Most of the existing research is based on software, there has not been a case of using hardware to implement the OLSR protocol. The core of implementing OLSR protocol based on FPGA (Field Programmable Gate Array) is the design of memory management table. This paper proposes a multi-link list design and FPGA implementation method, which effectively avoids the conflicts that will arise when using memory management tables.
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Acknowledgement
This work was supported in part by Science and Technology on Avionics Integration Laboratory and the Aeronautical Science Foundation of China (Grant No. 201955053002), the National Natural Science Foundations of CHINA (Grant No. 61871322, No. 61771392, No. 61771390, and No. 61501373), and Science and Technology on Avionics Integration Laboratory and the Aeronautical Science Foundation of China (Grant No. 20185553035).
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© 2021 ICST Institute for Computer Sciences, Social Informatics and Telecommunications Engineering
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Zhang, H., Li, B., Yan, Z., Yang, M. (2021). Multi-list Design and FPGA Implementation Method of OLSR protocol. In: Li, B., Li, C., Yang, M., Yan, Z., Zheng, J. (eds) IoT as a Service. IoTaaS 2020. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 346. Springer, Cham. https://doi.org/10.1007/978-3-030-67514-1_38
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DOI: https://doi.org/10.1007/978-3-030-67514-1_38
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