Abstract
With Moore’s Law ending and general-purpose processor speed plateauing, there are increasing interests and adoption of accelerators designed and built with FPGAs or SOCs. It is challenging to program the local memory of an accelerator. Past solutions are either based on scratchpad memory, which is entirely compiler managed, or on cache, which admits no direct program control.
This paper proposes a new approach similar to memory allocation where a program treats local memory as a heap and controls its allocation, while the hardware manages the remaining operations, e.g. data fetch and placement. The position paper describes this collaborative solution, discusses open research questions, and presents some preliminary results.
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Notes
- 1.
The exact algorithm of CARL, its optimality in assigning leases, and a set of results (more on this later) were described in a different document under submission. Here we address the remaining problems of CARL.
- 2.
Due to page limit, we only show 6 representative benchmarks instead of all 30 benchmarks (adi, cholesky, covariance, gemm, jacobi_1d, symm). These 6 are selected based on the shape of the curves. The other 24 have similar curves to one of the showed benchmarks. The calculation for cache space cost of CARL assumes the assigned lease for each reference only apply to its data blocks have reuses.
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Acknowledgments
The authors wish to thank Dr. Sreepathi Pai and Shawn Maag for the initial participation, the anonymous reviewers of LCPC and the workshop participants for the feedback. The financial support was provided in part by the National Science Foundation (Contract No. CNS-1909099, CCF-1717877).
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Chen, D., Ding, C., Patru, D. (2021). CLAM: Compiler Leasing of Accelerator Memory. In: Pande, S., Sarkar, V. (eds) Languages and Compilers for Parallel Computing. LCPC 2019. Lecture Notes in Computer Science(), vol 11998. Springer, Cham. https://doi.org/10.1007/978-3-030-72789-5_7
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