Hardware IP Protection Using Register Transfer Level Locking and Obfuscation of Control and Data Flow

Abstract

With the new advancement of Industry 4.0, there is raising concern over hardware intellectual property (IP) piracy and reverse engineering to an IP-based system-on-chip (SoC) design flow. In this chapter, we provide details on a register transfer level (RTL) hardware IP protection technique based on low-overhead key-based obfuscation of control and data flow. This technique achieves protection by transforming the RTL code to control data flow graph (CDFG). The transformed CDFG is integrated with a well-obfuscated finite state machine (FSM) of special structure, referred as “Mode-Control FSM” in a way that only a specific key sequence enables the normal functional behaviour. The chapter also discusses a basic metric to quantify the quality of obfuscation and provide theoretical analysis of the technique. We also discuss the integrated design flow along with simulation results of two open-source IP cores and low hardware footprint achieved by the technique. The chapter also provides a brief idea about the recent works on RTL-based hardware IP protection and future directions of research.