Abstract
FPGAs are part of a modern data-centre and are used as hardware accelerators, which allows to accelerate applications and adapting to the current compute requirements dynamically. Overlay architectures provide a flexible system, which enables the hardware accelerator to adapt its applications by exchanging (sub-)functions on run-time. Such overlay architectures usually consist of multiple run-time reconfigurable tiles. Multiple tiles can be connected to form an application-specific accelerator. In this paper, we present an AXI-Stream-compliant overlay architecture – called StreamGrid with advanced multi-stream routing architecture, memory (DDR4, HBM) access for the application, and a configuration and monitoring system. Furthermore, the impact of buffering strategies, grid-size, and data width of the AXI-Stream interface is explored in terms of resource utilization and the achievable clock frequency. The fastest configuration of the overlay architecture has a maximum clock frequency of 752 MHz on a Xilinx Alveo U280 FPGA Card. Furthermore, a case study of a database query engine is evaluated and compared to a static design with the same functionality. The raw execution performance is comparable for both design, but the set up times is now drastically reduced from several 10 min to less than 3 ms, efficiently enabling hardware-accelerated queries.
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Blochwitz, C., Philipp, L., Berekovic, M., Pionteck, T. (2021). StreamGrid - An AXI-Stream-Compliant Overlay Architecture. In: Derrien, S., Hannig, F., Diniz, P.C., Chillet, D. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2021. Lecture Notes in Computer Science(), vol 12700. Springer, Cham. https://doi.org/10.1007/978-3-030-79025-7_11
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