Abstract
Content-addressable memory (CAM) is a high-speed searching memory that provides the address of the input search key in one clock cycle. Traditional implementations of large CAMs on FPGAs with updatable memory elements are resource intensive requiring bigger and more expensive chips. Additional circuitry required for updating the CAM content is a major contributor to this which also impacts the overall clock performance of the circuit thus hampering the system throughput. To reduce the resource requirement, we investigate CAM implementation using read only memories (ROMs) and using partial reconfiguration (PR) to update their contents. Using a high-speed reconfiguration controller and bitstream compression, the reconfiguration overhead due to PR is offsetted. The results show 10% and 200% improvement in hardware resources and speed, respectively, compared to the state-of-the-art available FPGA-based TCAMs.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Ahmed, A., Park, K., Baeg, S.: Resource-efficient SRAM-based ternary content addressable memory. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(4), 1583–1587 (2017)
Garrault, P., Philofsky, B.: HDL coding practices to accelerate design performance. Technical Report. Xilinx Inc. (2006)
Irfan, M., Ullah, Z., Cheung, R.C.: D-TCAM: a high-performance distributed ram based TCAM architecture on FPGAs. IEEE Access 7, 96060–96069 (2019)
Karam, R., Puri, R., Ghosh, S., Bhunia, S.: Emerging trends in design and applications of memory-based computing and content-addressable memories. Proc. IEEE 103(8), 1311–1330 (2015)
Kornijcuk, V., et al.: Reconfigurable spike routing architectures for on-chip local learning in neuromorphic systems. Adv. Mater. Technol. 4(1), 1800345 (2019)
Nguyen, X.T., Nguyen, H.T., Pham, C.K.: A scalable high-performance priority encoder using 1D-array to 2D-array conversion. IEEE Trans. Circ. Syst. II Express Briefs 64(9), 1102–1106 (2017)
Reviriego, P., Ullah, A., Pontarelli, S.: PR-TCAM: efficient TCAM emulation on Xilinx FPGAs using partial reconfiguration. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 27(8), 1952–1956 (2019)
Somasundaram, M.: Circuits to generate a sequential index for an input number in a pre-defined list of numbers. US Patent 7,155,563, 26 Dec 2006
Srinivasavarma, V.S., Vidhyut, S.: A TCAM-based caching architecture framework for packet classification. ACM Trans. Embed. Comput. Syst. (TECS) 20(1), 1–19 (2020)
Tang, Q., Wang, Z., Guo, B., Zhu, L.H., Wei, J.B.: Partitioning and scheduling with module merging on dynamic partial reconfigurable FPGAs. ACM Trans. Reconfig. Technol. Syst. (TRETS) 13(3), 1–24 (2020)
Ullah, Z., Ilgon, K., Baeg, S.: Hybrid partitioned SRAM-based ternary content addressable memory. IEEE Trans. Circ. Syst. I Regul. Pap. 59(12), 2969–2979 (2012)
Vipin, K., Fahmy, S.A.: FPGA dynamic and partial reconfiguration: a survey of architectures, methods, and applications. ACM Comput. Surv. (CSUR) 51(4), 1–39 (2018)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2021 Springer Nature Switzerland AG
About this paper
Cite this paper
Irfan, M., Vipin, K., Cheung, R.C.C. (2021). On the Suitability of Read only Memory for FPGA-Based CAM Emulation Using Partial Reconfiguration. In: Derrien, S., Hannig, F., Diniz, P.C., Chillet, D. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2021. Lecture Notes in Computer Science(), vol 12700. Springer, Cham. https://doi.org/10.1007/978-3-030-79025-7_23
Download citation
DOI: https://doi.org/10.1007/978-3-030-79025-7_23
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-79024-0
Online ISBN: 978-3-030-79025-7
eBook Packages: Computer ScienceComputer Science (R0)