Timing Optimization for Virtual FPGA Configurations

Abstract

Fine-grained reconfigurable FPGA overlays, usually called virtual FPGAs, suffer from virtualization costs regarding area requirements and timing performance. Decreasing the area costs of such virtual FPGAs has been the focus of several research efforts over the past years, but adapting the (virtual) timing suffers from the contradiction of having to optimize properties with strong physical ties in an environment that is specifically designed to abstract them away.

This paper explores several methods to optimize the maximum operating frequency of the virtual FPGA ZUMA and its guest circuits despite this conflict using two complementary approaches: fine-tuned physical overlay design optimization through floorplanning in Xilinx’ design suite Vivado and delay-optimized virtual synthesis in the VTR tool flow. In our experimental results with virtual benchmark circuits, we respectively improve the operating frequency of a ${3\times 3}$ or a ${5\times 5}$ ZUMA architecture of up to $41\%$ and $65\%$ for individual benchmarks, and by $23\%$ and $31\%$ on average. Our results would also scale accordingly should future research uncover new potential to reduce the area cost further.

This work has been partially supported by the German Research Foundation (DFG) within the CRC901 “On-The-Fly Computing” under the project number 160364472.