Abstract
Design space exploration can be used to find a power-efficient architectural design for a given application, such as the best suited configuration of a heterogeneous system from soft cores of different types, given area and throughput constraints. We show how to integrate design space exploration into a static scheduling algorithm for a streaming task graph application with parallelizable tasks and solve the resulting combined optimization problem by an integer linear program (ILP). We demonstrate the improvements by our strategy with ARM big and LITTLE soft cores and synthetic task graphs.
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Notes
- 1.
In [10], we used parallel efficiency, i.e. speedup over core count, and separated the difference in performance between core types from the speedup by using an additional variable \(r_{i,j}\).
- 2.
We did not express the maximum width explicitly in Sect. 2 but included it in the definition of speedup.
- 3.
Please remember that also during task execution, power is composed from “idle” power and power on top, so that idle power mostly indicates static power.
- 4.
A smaller step than the area \(A_{LITTLE}\) of the smaller core would not change anything.
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Keller, J., Litzinger, S., Kessler, C. (2021). Combining Design Space Exploration with Task Scheduling of Moldable Streaming Tasks on Reconfigurable Platforms. In: Derrien, S., Hannig, F., Diniz, P.C., Chillet, D. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2021. Lecture Notes in Computer Science(), vol 12700. Springer, Cham. https://doi.org/10.1007/978-3-030-79025-7_7
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