Abstract
This chapter describes the use of SSA-based high-level program representations for the realization of the corresponding computations using hardware digital circuits. We begin by highlighting the benefits of using a compiler SSA-based intermediate representation in this hardware mapping process, using an illustrative example.
The subsequent sections describe hardware translation schemes for discrete hardware logic structures or datapaths of hardware circuits and outline several compiler transformations that benefit from SSA. We conclude with a brief survey of various hardware compilation efforts from both academia and industry that have adopted SSA-based internal representations.
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Notes
- 1.
It may be apparent that the original computation lacks any temporal specification in terms of the relative order in which data-independent operations can be carried out. Implementation variants exploit this property.
- 2.
A 2 × 1 multiplexer is a combinatorial circuit with two data inputs, a single output and a control input, where the control input selects which of the two data inputs is transmitted to the output.
- 3.
As a first approach, these registers are virtual, and then, after synthesis, some of them are materialized to physical registers in a process similar to register allocation in software-oriented compilation.
- 4.
Speculation is also possible in the temporal mode by activating the inputs and execution of multiple hardware blocks and is only limited by the available storage bandwidth to restore the input context in each block, which, in the spatial approach, is trivial.
- 5.
Under the scenarios of a spatial mapping and with the common disclaimers about static control-flow analysis.
- 6.
As with any SSA representation, variable names fulfil the referential transparency .
- 7.
An important issue in security-related aspects of the execution.
- 8.
A typical k-input LUT will include an arbitrary combinatorial functional block of those k inputs followed by an optional register element (e.g., Flip-Flop).
References
Böhm, W., et al. (2002). Mapping a single assignment programming language to reconfigurable systems. The Journal of Supercomputing, 21(2), 117–130.
Carter, L., et al. (1999). Predicated static single assignment. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques. PACT ’99 (p. 245).
de Ferrière, F. (2007). Improvements to the Psi-SSA representation. In Proceedings of the International Workshop on Software & Compilers for Embedded Systems. SCOPES ’07 (pp. 111–121).
Hagiescu, A., et al. (2009). A computing origami: Folding streams in FPGAs. In Proceedings of the Design Automation Conference. DAC ’09 (pp. 282–287).
Hormati, A., et al. (2008). Optimus: Efficient realization of streaming applications on FPGAs. In Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems. CASES ’08, pp. 41–50.
Metzgen, P., & Nancekievill, D. (2005). Multiplexer restructuring for FPGA implementation cost reduction. In Proceedings of the Design Automation Conference. DAC ’05 (pp. 421–426).
Stoutchinin, A., & de Ferrière, F. (2001). Efficient static single assignment form for predication. In Proceedings of the International Symposium on Microarchitecture. MICRO 34 (pp. 172–181).
Verma, A. K., Brisk, P., & Ienne, P. (2008). Dataflow transformations to maximize the use of carry-save representation in arithmetic circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(10), 1761–1774.
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Diniz, P.C., Brisk, P. (2022). Hardware Compilation Using SSA. In: Rastello, F., Bouchez Tichadou, F. (eds) SSA-based Compiler Design. Springer, Cham. https://doi.org/10.1007/978-3-030-80515-9_23
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DOI: https://doi.org/10.1007/978-3-030-80515-9_23
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