Abstract
Protecting computation systems against soft errors is expensive. Unoptimized soft error mitigation schemes can cause area, power, and performance overheads. Therefore, efficient fault-tolerant design should be guided by assessing the cost of developing reliable systems. We present a method to quantify and evaluate trade-offs to protect the system. Using gem5Panalyzer, the toolset we developed to estimate vulnerability factors of microprocessors, we conducted sweeps of Program Vulnerability Factor (PVF) masking to collect the PVF responses to instruction-level masking. We evaluated the confidence in PVF estimations made by gem5Panalyzer with multiple benchmarks from the MiBench suite. Then, we analyzed PVF-masking sweep results. The sensitivity of vulnerability improvement to mitigation techniques varies with the types of applications. When the instruction-level masking effect is 90%, time-averaged PVF reductions of selected benchmarks range from a high of 67% to a low of 10%. The differences in PVF reduction inform designers whether it is worth improving the masking level. As the masking factor is correlated with the efforts to implement mitigations, our method can help to optimize system design choices.
This material is based upon work supported by the National Science Foundation (NSF) under Grant No. CNS-1629853 and CNS-1629839.
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Qiu, H., Lin, BT., Olowogemo, S.A., Robinson, W.H., Limbrick, D.B. (2021). Evaluating Soft Error Mitigation Trade-offs During Early Design Stages. In: Hochberger, C., Bauer, L., Pionteck, T. (eds) Architecture of Computing Systems. ARCS 2021. Lecture Notes in Computer Science(), vol 12800. Springer, Cham. https://doi.org/10.1007/978-3-030-81682-7_14
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