Abstract
In the paper we review high-level synthesis software tools for special-purpose hardware circuit configurations for reconfigurable computer systems that consist of a numerous FPGA chips interconnected by a spatial communication system. The distinctive feature of the software tools is mapping of the source C-program into the completely parallel form (an information graph) which is transformed into the resource-independent parallel pipeline form and automatically scaled. As a result, a reasonable solution for an available hardware resource is generated. The information graph consists of tasks with data dependencies and different rates of data flows. The parallel-pipeline form is scaled by the methods of performance reduction with the same reduction coefficient for all subgraphs. Owing to this, the different fragments of the problem have the same data processing rate. The result of the transformations is balanced and reasonable computing structure of the whole problem with the same rate of data flows among its fragments. Besides, we review the results of the suggested methods applied to several implemented problems.
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Dordopulo, A.I., Levin, I.I., Gudkov, V.A., Gulenok, A.A. (2021). High-Level Synthesis of Scalable Solutions from C-Programs for Reconfigurable Computer Systems. In: Malyshkin, V. (eds) Parallel Computing Technologies. PaCT 2021. Lecture Notes in Computer Science(), vol 12942. Springer, Cham. https://doi.org/10.1007/978-3-030-86359-3_7
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