Abstract
Stream runtime verification (SRV) is a formalism to express monitors as relations between typed input streams (observations) and typed output streams (data verdicts). In SRV, the actual data operations are separated from the temporal dependencies, therefore generalizing monitoring algorithms for temporal logics into the computation of richer verdicts. In this paper we study a new and powerful feature, which consists of lifting the execution of monitors to functions that can be used in defining expressions of enclosing specifications. At runtime, the outer monitor invokes the inner monitor passing a list of input events, called a slice. We present nested monitors for synchronous streams and for real-time event streams, allowing the elegant description of many specifications of interest, while still keeping the resources bounded.
We formally describe nested monitors and slices, and illustrate the practical application in many real-life examples, including electrocardiogram analysis (QRS), quantitative Metric Temporal Logic and arbitrary robustness of Signal Temporal Logic specifications.
This work was funded in part by the Madrid Regional Government under project “S2018/TCS-4339 (BLOQUES-CM)”, by Spanish National Project “BOSCO (PGC2018-102210-B-100)”.
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Notes
- 1.
HLola and HStriver are available at http://github.com/imdea-software.
- 2.
Available at https://software.imdea.org/hlola/specs.html along with examples input and output events.
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Gorostiaga, F., Sánchez, C. (2021). Nested Monitors: Monitors as Expressions to Build Monitors. In: Feng, L., Fisman, D. (eds) Runtime Verification. RV 2021. Lecture Notes in Computer Science(), vol 12974. Springer, Cham. https://doi.org/10.1007/978-3-030-88494-9_9
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