Abstract
In ICISC 2020, 64-bit PIPO lightweight block cipher was presented. The main design goals of PIPO are the implementation-friendly and the ease of designing side-channel protection techniques. Until now, the performance of PIPO has been investigated only on 8-bit AVR environment. Thus, optimization strategies on various embedded devices need to be investigated for PIPO’s wide usage in various IoT applications. For filling this gap, in this paper, we present an optimized software implementation of PIPO cipher on 32-bit RISC-V processor being widely considered as an alternative embedded processor for ARM processors. For optimal performance, we propose several novel techniques: optimal register scheduling for minimizing the number of memory accesses, data parallel processing approach by using 32-bit register set, and combined internal process. In result, our software shows 128.5% improved performance on PIPO-64/128 basis than the simple ported version of RISC-V. In addition, our implementation showed 393.52% improvement over the encryption performance of the PIPO reference code, despite including the key scheduling process. As far as we know, this is the first optimal implementation of PIPO block cipher on RISC-V environment.
This work was partly supported by Institute of Information & communications Technology Planning & Evaluation (IITP) grant funded by the Korea government (MSIT) (No. A2021-0270, 6G autonomous security internalization-based technology research to ensure security quality at all times, 50%) and the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. 2019R1F1A1058494, 50%).
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Kwak, Y., Kim, Y., Seo, S.C. (2021). Parallel Implementation of PIPO Block Cipher on 32-bit RISC-V Processor. In: Kim, H. (eds) Information Security Applications. WISA 2021. Lecture Notes in Computer Science(), vol 13009. Springer, Cham. https://doi.org/10.1007/978-3-030-89432-0_15
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