Abstract
The Top-Down method makes it possible to identify bottlenecks as instructions traverse the CPU’s pipeline. Once bottlenecks are identified, incremental changes to the code can be made to mitigate the negative effects bottlenecks might have in performance. This is an iterative process that could potentially result in a more optimal use of CPU resources. It can be difficult to compare bottleneck metrics of the same program generated by different compilers running on the same system. Different compilers could potentially generate different instructions, arrange the instructions in different order, and require different number of cycles to execute the program. Ratios with relatively similar values could hide valuable information that could be used to identify differences in magnitude and influence of bottlenecks. To amplify magnitude differences of bottleneck metrics, we use the cycles required to complete the program as a reference point. We can then quantify the relative difference the effect a bottleneck has when compared with the bottleneck of the reference compiler. This study’s proposed approach is based on the Purchasing Power Parity theory, which is used by economists to compare the purchasing power of different currencies by comparing similar products. We show that this approach can give us more information on how effective each compiler is in using the CPU’s architectural features by comparing their respective bottlenecks. For example, using conventional methods, our measurements show that for the 363.swim benchmark, BackEnd Bound rates for GCC4 was 0.949, and 0.956 for GCC6 and GCC7 respectively. However, using the PPP normalization approach, we showed that there were differences of \(55.3\%\) for GCC6 and \(54.9\%\) for GCC7 over GCC4.
B. Swartz—Independent Researcher.
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References
The big mac index. https://www.economist.com/news/2020/01/15/the-big-mac-index
The gnu compiler collection website. http://gcc.gnu.org
Intel microarchitecture code named skylake events. https://download.01.org/perfmon/index/skylake.html
Intel vtune profiler. https://software.intel.com/content/www/us/en/develop/tools/vtune-profiler.html
Intel vtune profiler performance analysis cookbook. https://software.intel.com/content/www/us/en/develop/documentation/vtune-cookbook/top.html
The latte index: Using the impartial bean to value currencies. https://www.visualcapitalist.com/latte-index-currencies/
perf: Linux profiling with performance counters. http://perf.wiki.kernel.org
pmu-tools: Intel pmu profiling tools. https://github.com/andikleen/pmu-tools
Spec omp2012 documentation. https://spec.org/omp2012/Docs/index.html
Spec omp2012 results. https://www.spec.org/omp2012/results/
Ayers, G., Ahn, J.H., Kozyrakis, C., Ranganathan, P.: Memory hierarchy for web search. In: 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 643–656 (2018)
Cabezas, V.C., Püschel, M.: Extending the roofline model: bottleneck analysis with microarchitectural constraints. In: 2014 IEEE International Symposium on Workload Characterization (IISWC). pp. 222–231 (2014)
Clements, K.: Currencies, Commodities and Consumption. Cambridge University Press, Cambridge (2013)
Jöreskog, K., Wold, H.: Systems under indirect observation: causality, structure, prediction. No. no. 139, pt. 2 in Contributions to Economic Analysis, North-Holland (1982)
Laurenzano, M.A., Tiwari, A., Cauble-Chantrenne, A., Jundt, A., Ward, W.A., Campbell, R., Carrington, L.: Characterization and bottleneck analysis of a 64-bit armv8 platform. In: 2016 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 36–45 (2016)
McKenney, P.E.: Differential profiling. In: MASCOTS 1995. Proceedings of the Third International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, pp. 237–241 (1995)
Müller, M.S., et al.: SPEC OMP2012 — an application benchmark suite for parallel systems using OpenMP. In: Chapman, B.M., Massaioli, F., Müller, M.S., Rorro, M. (eds.) IWOMP 2012. LNCS, vol. 7312, pp. 223–236. Springer, Heidelberg (2012). https://doi.org/10.1007/978-3-642-30961-8_17
Williams, S., Waterman, A., Patterson, D.: Roofline: an insightful visual performance model for multicore architectures. Commun. ACM 52(4), 65–76 (2009)
Yasin, A.: A top-down method for performance analysis and counters architecture. In: 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 35–44 (2014)
Yasin, A., Ben-Asher, Y., Mendelson, A.: Deep-dive analysis of the data analytics workload in cloudsuite. In: 2014 IEEE International Symposium on Workload Characterization (IISWC), pp. 202–211 (2014)
Yasin, A., Haj-Yahya, J., Ben-Asher, Y., Mendelson, A.: A metric-guided method for discovering impactful features and architectural insights for skylake-based processors. ACM Trans. Archit. Code Optim. 16(4) (2019). https://doi.org/10.1145/3369383
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Huerta, Y.A., Swartz, B., Lilja, D.J. (2022). Enhancing the Top-Down Microarchitectural Analysis Method Using Purchasing Power Parity Theory. In: Chapman, B., Moreira, J. (eds) Languages and Compilers for Parallel Computing. LCPC 2020. Lecture Notes in Computer Science(), vol 13149. Springer, Cham. https://doi.org/10.1007/978-3-030-95953-1_12
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