Abstract
As spatial and temporal resolutions of scientific instruments improve, the explosion in the volume of data produced is becoming a key challenge. It can be a critical bottleneck for integration between scientific instruments at the edge and high-performance computers/emerging accelerators. Placing data compression or reduction logic close to the data source is a possible approach to solve the bottleneck. However, the realization of such a solution requires the development of custom ASIC designs, which is still challenging in practice and tends to produce one-off implementations unusable beyond the initial intended scope. Therefore, as a feasibility study, we have been investigating a design workflow that allows us to explore algorithmically complex hardware designs and develop reusable hardware libraries for the needs of scientific instruments at the edge. Our vision is to cultivate our hardware development capability for streaming/dataflow hardware components that can be placed close to the data source to enable extreme data-intensive scientific experiments or environmental sensing. Furthermore, reducing data movement is essential to improving computing performance in general. Therefore, our co-design efforts on streaming hardware components can benefit computing applications other than scientific instruments. This vision paper discusses hardware specialization needs in scientific instruments and briefly reviews our progress leveraging the Chisel hardware description language and emerging open-source hardware ecosystems, including a few design examples.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
Notes
- 1.
The performance offered by a carefully optimized HLS implementation is comparable to that of an HDL implementation; however, resource usage is still in question.
- 2.
An open community for analog and mixed-signal IC and IP development and commercialization https://efabless.com/.
- 3.
Currently, only a select few technology nodes can be targeted with open-source EDA tools.
- 4.
FPGA deployments may require pipelining for the sake of achieving low latency.
- 5.
Significant lines of code, i.e., excluding comments.
References
Hameed, R., et al.: Understanding sources of inefficiency in general-purpose chips. In: Proceedings of the 37th Annual International Symposium on Computer Architecture, pp. 37–47 (2010)
Ovtcharov, K., Ruwase, O., Kim, J.-Y., Fowers, J., Strauss, K., Chung, E.S.: Accelerating deep convolutional neural networks using specialized hardware. Microsoft Res. Whitepaper 2(11), 1–4 (2015)
Kahng, A.B.: AI system outperforms humans in designing floorplans for microchips. Nature 594(7862), 183–185 (2021)
Hammer, M., Yoshii, K., Miceli, A.: Strategies for on-chip digital data compression for X-ray pixel detectors. J. Instrum. 16, P01025 (2021)
Genc, H., et al.: Gemmini: an agile systolic array generator enabling systematic evaluations of deep-learning architectures (2019)
Farshchi, F., Huang, Q., Yun, H.: Integrating NVIDIA Deep Learning Accelerator (NVDLA) with RISC-V SoC on FireSim. In: 2019 2nd Workshop on Energy Efficient Machine Learning and Cognitive Computing for Embedded Applications (EMC2), pp. 21–25 (2019)
Zhang, Y., Pan, J., Liu, X., Chen, H., Chen, D., Zhang, Z.: FracBNN: accurate and FPGA-efficient binary neural networks with fractional activations. In: The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (2021)
Duarte, J., et al.: Fast inference of deep neural networks in FPGAs for particle physics. J. Instrum. 13(07), P07027 (2018)
Eldridge, S., Waterland, A., Seltzer, M., Appavoo, J., Joshi, A.: Towards general-purpose neural network computing. In: 2015 International Conference on Parallel Architecture and Compilation, PACT 2015, San Francisco, CA, USA, 18–21 October 2015, pp. 99–112 (2015)
Liu, Z., et al.: BraggNN: fast X-ray Bragg peak analysis using deep learning. arXiv preprint arXiv:2008.08198 (2021)
Golson, S., Clark, L.: Language wars in the 21st century: verilog versus vhdl–revisited. Synopsys Users Group (SNUG) (2016)
Kung, H.T., Leiserson, C.E.: Systolic arrays for (VLSI). Technical report, Department of Computer Science, Carnegie-Mellon University, Pittsburgh, Pennsylvania (1978)
Kwon, H., Krishna, T.: OpenSMART: single-cycle multi-hop NoC generator in BSV and Chisel. In: 2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 195–204. IEEE (2017)
Ueno, T., Sano, K., Yamamoto, S.: Bandwidth compression of floating-point numerical data streams for FPGA-based high-performance computing. ACM Trans. Reconfigurable Technol. Syst. 10, 1–22 (2017)
Lee, Y., et al.: An agile approach to building RISC-V microprocessors. IEEE Micro 36(2), 8–20 (2016)
Bachrach, J., et al.: Chisel: constructing hardware in a Scala embedded language. In: DAC Design Automation Conference, pp. 1212–1221 (2012)
Bachrach, J.J., Asanović, K.: Chisel 3.0 tutorial. Technical report, EECS Department, UC Berkeley (2017)
Schoeberl, M.: Digital Design in Chisel. Kindle Direct Publishing, Seattle (2020)
Odersky, M., Spoon, L., Venners, B.: Programming in Scala. Artima Inc., Walnut Creek (2008)
Mosanu, S., Guo, X., El-Hadedy, M., Anghel, L., Stan, M.: Flexi-AES: a highly-parameterizable cipher for a wide range of design constraints. In: 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), p. 338. IEEE (2019)
Arcas-Abella, O., et al.: An empirical evaluation of high-level synthesis languages and tools for database acceleration. In: 2014 24th International Conference on Field Programmable Logic and Applications (FPL), pp. 1–8. IEEE (2014)
Asanović, K., et al.: The rocket chip generator. Technical report, UCB/EECS-2016-17, EECS Department, University of California, Berkeley (2016)
Celio, C., Chiu, P.-F., Nikolic, B., Patterson, D.A., Asanovic, K.: BOOMv2: an open-source out-of-order RISC-V core. In: First Workshop on Computer Architecture Research with RISC-V (CARRV) (2017)
Bailey, S., et al.: A 28nm FDSOI 8192-point digital ASIC spectrometer from a Chisel generator. In: 2018 IEEE Custom Integrated Circuits Conference (CICC), pp. 1–4. IEEE (2018)
Cass, S.: Taking AI to the edge: Google’s TPU now comes in a maker-friendly package. IEEE Spectr. 56(5), 16–17 (2019)
Lockhart, D., et al.: Experiences building edge TPU with Chisel. In: 2018 Chisel Community Conference (2018)
Di Tucci, L., Conficconi, D., Comodi, A., Hofmeyr, S., Donofrio, D., Santambrogio, M.D.: A parallel, energy efficient hardware architecture for the merAligner on FPGA using Chisel HCL. In: 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pp. 214–217. IEEE (2018)
Serre, F., Püschel, M.: A DSL-based FFT hardware generator in Scala. In: 2018 28th International Conference on Field Programmable Logic and Applications (FPL), pp. 315–3157. IEEE (2018)
Nowatzki, T., Gangadhar, V., Ardalani, N., Sankaralingam, K.: Stream-dataflow acceleration. In: 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), pp. 416–429. IEEE (2017)
Prabhakar, R., et al.: Plasticine: a reconfigurable architecture for parallel patterns. In: 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), pp. 389–402. IEEE (2017)
Amid, A., et al.: Chipyard: integrated design, simulation, and implementation framework for custom SoCs. IEEE Micro 40(4), 10–21 (2020)
Asanovic, K., Patterson, D.A., Celio, C.: The berkeley out-of-order machine (BOOM): an industry-competitive, synthesizable, parameterized RISC-V processor. Technical report, University of California at Berkeley Berkeley United States (2015)
Wang, A.: Agile design of generator-based signal processing hardware. Ph.D. thesis, EECS Department, University of California, Berkeley (2019)
Dobis, A., et al.: Open-source verification with Chisel and Scala (2021)
Snyder, W.: Verilator: open simulation-growing up. DVClub Bristol (2013)
Truong, L., Hanrahan, P.: A golden age of hardware description languages: applying programming language techniques to improve design productivity. In: 3rd Summit on Advances in Programming Languages (SNAPL 2019), Schloss Dagstuhl-Leibniz-Zentrum fuer Informatik (2019)
Hennessy, J., Patterson, D.: A new golden age for computer architecture: domain-specific hardware/software co-design, enhanced. In: ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA) (2018)
Asanović, K., Patterson, D.A.: Instruction sets should be free: the case for RISC-V. Technical report UCB/EECS-2014-146, EECS Department, University of California, Berkeley (2014)
Fatollahi-Fard, F., Donofrio, D., Michelogiannakis, G., Shalf, J.: OpenSoC fabric: on-chip network generator: using Chisel to generate a parameterizable on-chip interconnect fabric. In: Proceedings of the 2014 International Workshop on Network on Chip Architectures, pp. 45–50 (2014)
Wolf, C., Glaser, J., Kepler, J.: Yosys - a free Verilog synthesis suite. In: Proceedings of the 21st Austrian Workshop on Microelectronics (Austrochip) (2013)
Izraelevitz, A., et al.: Reusability is FIRRTL ground: hardware construction languages, compiler frameworks, and transformations. In: 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 209–216. IEEE (2017)
Ansell, T., Saligane, M.: The missing pieces of open design enablement: a recent history of Google efforts (invited paper). In: 2020 IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp. 1–8. IEEE (2020)
Edwards, R.T., Shalan, M., Kassem, M.: Real silicon using open-source EDA. IEEE Des. Test 38, 38–44 (2021)
Czajkowski, T.S., et al.: From OpenCL to high-performance hardware on FPGAs. In: 22nd International Conference on Field Programmable Logic and Applications (FPL), pp. 531–534. IEEE (2012)
Decaluwe, J.: MyHDL: a python-based hardware description language. Linux J. 127, 84–87 (2004)
Migen, a python toolbox for building complex digital hardware. https://github.com/m-labs/migen
Baaij, C.: C\(\lambda \)ash: from Haskell to hardware (2009)
Charles, P.: SpinalHDL (2016). https://github.com/SpinalHDL/SpinalHDL
Koeplinger, D., et al.: Spatial: a language and compiler for application accelerators. In: Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation, pp. 296–311 (2018)
Hashemian, R.: Design and hardware construction of a high speed and memory efficient Huffman decoding. In: IEEE International Conference on Consumer Electronics, pp. 74–75. IEEE (1994)
Strempfer, S., Yoshii, K., Hammer, M., Bycul, D., Miceli, A.: Designing a streaming data coalescing architecture for scientific detector ASICs with variable data velocity. arXiv preprint arXiv:2008.08198 (2021)
Acknowledgments
We thank Ian Foster and Kyle Chard for supporting this exciting collaboration between Argonne National Laboratory and the University of Chicago Department of Computer Science. We thank Pete Beckman and Alec Sandy for encouraging this multidisciplinary collaboration between the X-ray Science Division (XSD) and the Mathematics and Computer Science (MCS) Division at Argonne National Laboratory. We also thank two anonymous referees for their useful comments. We thank Gail Pieper for editing this manuscript. The material is based upon work supported by Laboratory Directed Research and Development (LDRD 2021-0072) funding from Argonne National Laboratory, provided by the Director, Office of Science, of the U.S. Department of Energy under contract DE-AC02-06CH11357.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2022 Springer Nature Switzerland AG
About this paper
Cite this paper
Yoshii, K., Sankaran, R., Strempfer, S., Levental, M., Hammer, M., Miceli, A. (2022). A Hardware Co-design Workflow for Scientific Instruments at the Edge. In: Nichols, J., et al. Driving Scientific and Engineering Discoveries Through the Integration of Experiment, Big Data, and Modeling and Simulation. SMC 2021. Communications in Computer and Information Science, vol 1512. Springer, Cham. https://doi.org/10.1007/978-3-030-96498-6_12
Download citation
DOI: https://doi.org/10.1007/978-3-030-96498-6_12
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-96497-9
Online ISBN: 978-3-030-96498-6
eBook Packages: Computer ScienceComputer Science (R0)