Hardware Description Language Enhancements for High Level Synthesis of Hardware Accelerators

Abstract

High level synthesis of hardware accelerators is one of the many complex hardware operations that unfortunately cannot be efficiently performed with languages like Verilog or VHDL. Hardware designers, in order to bridge these gaps present in traditional HDLs, have taken to implementing such high-level hardware operations using functional programming (FP) languages or languages derived from FP languages. This is because FP languages (or their derivatives) have many important features like MapReduce, Immutable variables and Lazy evaluation. Today, only languages like Chisel, MyHDL or Haskell are used to perform high-level hardware operations. This obviously presents itself as a learning curve that hardware designers and experts have to go through in addition to learning Verilog or VHDL. This paper presents a novel approach that aims to take the standard syntax of Verilog and provide necessary enhancements for it to support basic functional programming constructs like Chain and Tree. The main component of this approach is the translation of the enhanced Verilog syntax to standard Verilog. This will be achieved using relevant Python libraries, methods and syntactic macros.