Abstract
Current CMOS technology suffers from low device density and high power dissipation due to tremendous enhancement of device scaling. Quantum-dot Cellular Automata (QCA) is alternative nanotechnology to overcome these drawbacks. A cell containing four quantum dots and two electrons is a fundamental element for logic circuit realization in QCA. In QCA, clocking plays a vital role in the proper synchronization and flow of information along with the scalability of the QCA circuit. In addition, regular clocking diminishes the fabrication challenges of the nanoscale era. On the other hand, defects remain an issue in nanoscale circuit realization. This work aims to analyze the performance of underlying clocking schemes in terms of fault-tolerant capability. A full adder circuit is realized using different clocking schemes, and the HDLQ and QCADesigner simulators are used for this purpose. According to experimental results, Zig-Zag clocking exhibits better performance under cell deposition defects, whereas RES clocking stands at the top in the case of HDLQ analysis.
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References
Blair, E., Lent, C.: Clock topologies for molecular quantum-dot cellular automata. J. Low Power Electr. Appli. 8(3), 31 (2018)
Campos, C.A.T., Marciano, A.L., Neto, O.P.V., Torres, F.S.: Use: A universal, scalable, and efficient clocking scheme for QCA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(3), 513–517 (2015)
Fazzion, E., Fonseca, O.L.H.M., Nacif, J.A.M., Vilela Neto, O.P., Fernandes, A.O., Silva, D.S.: A quantum-dot cellular automata processor design. In: 2014 27th Symposium on Integrated Circuits and Systems Design (SBCCI), pp. 1–7 (2014)
Fijany, A., Toomarian, B.N.: New design for quantum dots cellular automata to obtain fault tolerant logic gates. J. Nanopart. Res. 3(1), 27–37 (2001)
Goswami, M., Mondal, A., Mahalat, M.H., Sen, B., Sikdar, B.K.: An efficient clocking scheme for quantum-dot cellular automata. Int. J. Electron. Lett. 83–96 (2019)
Karim, F., Walus, K.: Efficient simulation of correlated dynamics in quantum-dot cellular automata (QCA). IEEE Trans. Nanotechnol. 13(2), 294–307 (2014)
Lent, C.S., Tougaw, P.D.: A device architecture for computing with quantum dots. Proc. IEEE 85(4), 541–557 (1997)
Mohammadi, M., Mohammadi, M., Gorgin, S.: An efficient design of full adder in quantum-dot cellular automata (QCA) technology. Microelectron. J. 50, 35–43 (2016)
Ottavi, M., Schiano, L., Lombardi, F., Tougaw, D.: Hdlq: a hdl environment for QCA design. J. Emerg. Technol. Comput. Syst. 2(4), 243–261 (2006)
Pal, J., Bhattacharjee, S., Saha, A.K., Dutta, P.: Study on temperature stability and fault tolerance of adder in quantum-dot cellular automata. In: 2019 5th international conference on signal processing, computing and control (ispcc), pp. 69–74. IEEE (2019)
Pal, J., Pramanik, A.K., Sharma, J.S., Saha, A.K., Sen, B.: An efficient, scalable, regular clocking scheme based on quantum dot cellular automata. In: IAnalog Integrated Circuits and Signal Processing, pp. 659–670 (2021)
Pramanik, A.K., Bhowmik, D., Pal, J., Sen, P., Saha, A.K., Sen, B.: Towards the realization of regular clocking-based QCA circuits using genetic algorithm. Comput. Elect. Eng. 97, 107640 (2022)
Pramanik, A.K., Pal, J., Sen, B.: Impact of genetic algorithm on low power QCA logic circuit with regular clocking. In: Proceedings of First Asian Symposium on Cellular Automata Technology, pp. 191–203. Springer Nature, Singapore (2022), https://doi.org/10.1007/978-981-19-0542-1_14
Ravindran, R.S.E., Priyadarshini, K.M., Teja, D.P.M.P., Chakravarthy, P.N., Teja, P.D.: Design of ram using quantum cellular automata (QCA) designer. Int. J. Sci. Technol. Res. 8, 1385–1390 (2019)
Sen, B., Rajoria, A., Sikdar, B.K.: Design of efficient full adder in quantum-dot cellular automata. Sci. World J. 2013 (2013)
Tahoori, M., Huang, J., Momenzadeh, M., Lombardi, F.: Testing of quantum cellular automata, Nanotechnology. IEEE Trans. 3, 432–442 (2005)
Wang, L., Xie, G., Zhu, R., Yu, C.: An optimized clocking scheme for nanoscale quantum-dot cellular automata circuit. In: 2019 IEEE 14th International Conference on Nano/Micro Engineered and Molecular Systems (NEMS), pp. 336–341. IEEE (2019)
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Pramanik, A.K., Pal, J., Sikdar, B.K., Sen, B. (2022). Performance Analysis of Regular Clocking Based Quantum-Dot Cellular Automata Logic Circuit: Fault Tolerant Approach. In: Chopard, B., Bandini, S., Dennunzio, A., Arabi Haddad, M. (eds) Cellular Automata. ACRI 2022. Lecture Notes in Computer Science, vol 13402. Springer, Cham. https://doi.org/10.1007/978-3-031-14926-9_17
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