Abstract
Limitations on Complementary Metal Oxide Semiconductor (CMOS) technology scaling combined with the increasing demand for emerging applications requiring high computing and storage capabilities pose significant challenges to device technologies and computer architectures. From the point of view of device technology, memristive devices have become the most promising candidate to complement and/or replace CMOS technology. The key advantages are the memristive device’s CMOS manufacturing process compatibility, zero standby power consumption, high scalability and density, as well as the memristive device’s capability to implement high-density memories as well as new computing paradigms. Despite all these advantages, these novel devices are also susceptible to manufacturing deviations that may cause faulty behaviors not observed in CMOS technology, significantly increasing the test complexity. In such context, this paper presents a Design-for-Testability (DfT) strategy able to detect traditional as well as unique faults in Resistive Random Access Memories (RRAMs). In more detail, an on-chip sensor able to perform electrical measurements, while performing a predefined operating sequence, was implemented using an X-Fab technology library. The obtained results demonstrate the proposed strategy’s capability to detect unique faults in RRAM cells. Finally, the paper provides a discussion about introduced overheads and implementation granularity.
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Acknowledgment
This work was supported by the Federal Ministry of Education and Research (BMBF, Germany) within the NEUROTEC I & II projects 16ES1134 and 16ME0399.
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Copetti, T.S., Gemmeke, T., Poehls, L.M.B. (2022). A DfT Strategy for Detecting Emerging Faults in RRAMs. In: Grimblatt, V., Chang, C.H., Reis, R., Chattopadhyay, A., Calimera, A. (eds) VLSI-SoC: Technology Advancement on SoC Design. VLSI-SoC 2021. IFIP Advances in Information and Communication Technology, vol 661. Springer, Cham. https://doi.org/10.1007/978-3-031-16818-5_5
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