Abstract
Dataflow architecture is a promising parallel computing platform with high performance, efficiency and flexibility. Dataflow mapping algorithm offloads programs onto dataflow hardware, which has a significant impact on the performance of the architecture. Dataflow mapping methods in previous studies are hardly efficient as they rarely consider the requirements of routing resources. In this paper, we propose a routing-aware mapping algorithm by combining hardware resources and dataflow graph characteristics to explore better mapping schemes. Our method first focuses on the influence of predecessor and successor nodes when mapping a node, and then comprehensively considers the competition of computing resources and the routing cost, to find the mapping solution with the lowest overhead. Experiments demonstrate that our method can achieve up to 2.06\(\times \) performance improvement and 12.8% energy consumption reduction compared to state-of-the-art methods.
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Acknowledgments
This work was partly supported by National Natural Science Foundation of China (Grant No. 61732018 and 61872335), Austrian-Chinese Cooperative R &D Project (FFG and CAS) (Grant No. 171111KYSB20200002), CAS Project for Young Scientists in Basic Research (Grant No. YSBR-029), CAS Project for Youth Innovation Promotion Association, Zhejiang Lab (Grant No. 2022PB0AB01), and the project of the state grid corporation of China in 2020 “Integration Technology Research and Prototype Development for High End Controller Chip” (Grant No. 5700-202041264A-0-0-00).
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Fan, Z., Li, W., Liu, T., An, X., Ye, X., Fan, D. (2022). A Routing-Aware Mapping Method for Dataflow Architectures. In: Liu, S., Wei, X. (eds) Network and Parallel Computing. NPC 2022. Lecture Notes in Computer Science, vol 13615. Springer, Cham. https://doi.org/10.1007/978-3-031-21395-3_1
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DOI: https://doi.org/10.1007/978-3-031-21395-3_1
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