Abstract
One-dimensional convolutional neural network (1D-CNN) has a major advantage of low-cost implementation on edge devices, for time series classification. However, for the edge devices working in real-time computing (RTC) systems, the nonconcurrent availability of input signals leads to a more complex computing process and a bigger challenge to satisfy the resource and timing constraints. In this paper, an energy-efficient high-performance 1D-CNN architecture is proposed for edge inference of RTC systems, which performs 1D-CNN operations element-wisely and simultaneously when the input sequence is streamed. We present a data reuse scheme to maximally reduce the computational and memory resources, based on the generation of 1D-CNN feature maps during RTC. A compiler is developed to generate the hardware architecture in pipeline, for any given 1D-CNN model. We implement our proposed architecture by a 65-nm CMOS technology, and show this design realizes up to 1.72 TOPs/W power efficiency. Regarding computational latency, our design can outperform state-of-the-art CNN accelerators with a reduction of more than one order of magnitude.
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Acknowledgement
The work was supported by State Key Laboratory of Computer Architecture (ICT, CAS) under Grant No. CARCH201909.
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Liu, X., Sai, G., Duan, S. (2022). Hardware Acceleration for 1D-CNN Based Real-Time Edge Computing. In: Liu, S., Wei, X. (eds) Network and Parallel Computing. NPC 2022. Lecture Notes in Computer Science, vol 13615. Springer, Cham. https://doi.org/10.1007/978-3-031-21395-3_18
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DOI: https://doi.org/10.1007/978-3-031-21395-3_18
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