Abstract
Nanoscale device design beyond 20 nm technology nodes constrain material thermal conductivity and exacerbates the self-heating phenomenon in Multigate MOSFETs such as FinFET and Nanosheet. The presence of dielectric under the source and drain in stacked Nanoheet Transistors (SNT) exacerbates the Self Heating Effect because it breaks the heat flow path due to low thermal conductivity. From a performance and reliability standpoint, this research focuses on the thermal aspect of the SNT after insertion of the dielectric under the source and drain. The effect of dielectric insertion under the source and drain on lattice temperature was investigated using electrothermal simulation of single and double stack nanosheet transistors. The effects of dielectric insertion thickness under the source and drain on the substrate, as well as SNT channel temperature analyzed and its variation with width and extension length of SNT are explained.
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Kumar, V., Patel, J., Datta, A., Dasgupta, S. (2022). FEM Modeling of Thermal Aspect of Dielectric Inserted Under Source & Drain of 5 nm Nanosheet. In: Shah, A.P., Dasgupta, S., Darji, A., Tudu, J. (eds) VLSI Design and Test. VDAT 2022. Communications in Computer and Information Science, vol 1687. Springer, Cham. https://doi.org/10.1007/978-3-031-21514-8_1
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DOI: https://doi.org/10.1007/978-3-031-21514-8_1
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