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Electro-Thermal Analysis of Vertically Stacked Gate All Around Nano-sheet Transistor

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VLSI Design and Test (VDAT 2022)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 1687))

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Abstract

This paper presents optimization of drain/source extension length of 5 nm node Nano-sheet Transistor (NSHT) using a fully-calibrated TCAD platform. A 12 nm extension length shows a 49.5% increase in ION/IOFF compared to NSHT with a 5 nm extension length. For the extension lengths longer than 12 nm, ION/IOFF begins degrading. SHEs effects are worse for higher supply voltages (VDD). An increase in VDD from 0.7 V to 1.5 V results in a 50.89% increase in peak lattice temperature for the NSHT. Also, at VDD = 1.5 V, the ON current (ION) degrades by 12.27% when SHEs are considered. Finally, the effect of different spacer dielectric materials on SHEs is studied for the optimized NSHT device. The ION degradations of 11.73%, 10.68%, and 12.27% are observed for HfO2, Si3N4, and SiO2, respectively. The use of spacer dielectric with larger thermal conductivity is observed as a possible remedy to tackle the ION degradation.

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Authors and Affiliations

  1. Deptartment of Electronics Engineering, National Institute of Technology, Srinagar Garhwal, Uttarakhand, 246174, India

    Arvind Bisht, Yogendra Pratap Pundir & Pankaj Kumar Pal

  2. Deptartment of Electronics and Communication Engineering, HNB Garhwal University, Srinagar Garhwal, Uttarakhand, 246174, India

    Yogendra Pratap Pundir

Authors
  1. Arvind Bisht
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  2. Yogendra Pratap Pundir
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  3. Pankaj Kumar Pal
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Corresponding author

Correspondence to Yogendra Pratap Pundir .

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Editors and Affiliations

  1. Department of Electrical Engineering, Indian Institute of Technology Jammu, Jammu, India

    Ambika Prasad Shah

  2. Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, India

    Sudeb Dasgupta

  3. Department of Electronics Engineering, Sardar Vallabhbhai National Institute of Technology Surat, Surat, India

    Anand Darji

  4. Department of Computer Science and Engineering, Indian Institute of Technology Tirupati, Tirupati, India

    Jaynarayan Tudu

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Bisht, A., Pundir, Y.P., Pal, P.K. (2022). Electro-Thermal Analysis of Vertically Stacked Gate All Around Nano-sheet Transistor. In: Shah, A.P., Dasgupta, S., Darji, A., Tudu, J. (eds) VLSI Design and Test. VDAT 2022. Communications in Computer and Information Science, vol 1687. Springer, Cham. https://doi.org/10.1007/978-3-031-21514-8_12

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  • DOI: https://doi.org/10.1007/978-3-031-21514-8_12

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-031-21513-1

  • Online ISBN: 978-3-031-21514-8

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