Abstract
Arbiter PUFs (APUFs) are a good choice for their lightweight configuration but vulnerable to Machine Learning (ML) based attacks. This paper presents a feed-forward PUF (FF PUF) to increase the resistivity by adding a non-linear component in the feed-forward loop. The non-linear component is designed by XORing the response of two consecutive stages of conventional FF PUF and feeding it as a challenge to an intermediate stage. To decrease the susceptibility to various ML-based attacks, the proposed feed-forward XOR PUF (FFXOR PUF) is designed by XORing the response of multiple FF PUFs. The performance of the proposed FFXOR PUF is compared with the existing APUF and XOR APUF. The minimum prediction accuracy of the proposed FFXOR PUF with 5 levels is achieved 51.6%(SVM) and 50.43%(ANN). Also, the training time is increased by 3.1 times in comparison with the conventional XOR APUF. Different PUF architectures such as APUF, XOR APUF and the proposed FFXOR PUF with 32-stages are implemented on Xilinx Zynq-7000 (Zedboard) FPGA.
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This work is supported and funded by Science and Engineering Research Board (SERB), Department of Science and Technology, Government of India under the project grant number CRG/2021/007437.
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Gupta, A., Manhas, S., Das, B.P. (2022). Highly Non-linear Feed-Forward Arbiter PUF Against Machine Learning Attacks. In: Shah, A.P., Dasgupta, S., Darji, A., Tudu, J. (eds) VLSI Design and Test. VDAT 2022. Communications in Computer and Information Science, vol 1687. Springer, Cham. https://doi.org/10.1007/978-3-031-21514-8_21
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