Abstract
Recent trends in wearable ECG monitoring devices are focused on the early diagnosis of heart diseases. However, the artifact generated during ECG signal acquisition reduces the performance of these devices. Many methods available for artifact suppression have a limitation on hardware implementation due to high complexity. This paper analyzes a two-stage reference-free active noise cancellation (ANC) adaptive filter for optimum step-size and filter length selection to denoise the ambulatory ECG signal. The ECG denoising results show that the proposed method gives 16.04% more average output SNR and 10.61% more average MSE reduction than the existing reference-free adaptive filter design. Further, the analysis is carried out for a two-stage adaptive filter hardware design. The real-time hardware testing is performed on a spartan3E FPGA board. The results show that implemented hardware only occupies 465 slices, which is \(9.46\%\) lower resource utilization compared to the existing method on Virtex-7 FPGA. Moreover, the hardware ASIC implementation shows only 0.66 \((mm)^2\) area utilization and total 0.5 mW power consumption at 1.8 V supply and 5 kHz sampling frequency.
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Prajapati, P., Darji, A. (2022). Hardware Design of Two Stage Reference Free Adaptive Filter for ECG Denoising. In: Shah, A.P., Dasgupta, S., Darji, A., Tudu, J. (eds) VLSI Design and Test. VDAT 2022. Communications in Computer and Information Science, vol 1687. Springer, Cham. https://doi.org/10.1007/978-3-031-21514-8_26
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