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Signal Integrity and Power Loss Analysis for Different Bump Structures in Cylindrical TSV

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VLSI Design and Test (VDAT 2022)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 1687))

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Abstract

The selection of a suitable bump shape is critical to the performance of a 3D packaging system. The most widely used bump shape (cylindrical) is facing significant reliability issues, including coefficient of thermal expansion (CTE) mismatch, stress and power loss. Bump with a tapered shape have procured a lot of attention recently because of their low volume fraction and coupling capacitance, which can significantly minimize stress and crosstalk related delay. In order to quantify the effective CTE and stress of different solder structures the bump/underfill composite assembly is quantitatively studied using 3D unit-cell technique, which takes evenly distributed bump in the underfill. The temperature-dependent effective CTE of the evenly distributed bump incorporating the volume fraction can be used for the analysis of the stress issues. Additionally, for the analysis of the power loss, the analytical π based impedance network is proposed. The model was successfully verified by EM simulation under the different frequency range. Furthermore, a distinctive electromagnetic (EM) based model is used to analyze the NEXT (Near end) and FEXT (Far end) crosstalk delay using coupled bump arrangement at 32 nm technology. Using Computer Simulation Microwave Studio (CST MWS) industry-standard EM simulations tool, the crosstalk induced delay is obtained upto 20 GHz operating frequencies for different bump architectures i.e. cylindrical, spherical and tapered. Considering a tapered bump, a substantial improvement in NEXT, FEXT, and CTE at 32 nm technology is observed as 3.39%, 4.02%, 7.03%, 8.08% 11.88%, and 40.18% respectively compared to the spherical and cylindrical bump.

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Authors and Affiliations

  1. International Institute of Information Technology, Naya Raipur, 493661, Chhattisgarh, India

    Shivangi Chandrakar, Kunal Kranti Das, Deepika Gupta & Manoj Kumar Majumder

Authors
  1. Shivangi Chandrakar
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  2. Kunal Kranti Das
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  3. Deepika Gupta
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  4. Manoj Kumar Majumder
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Corresponding author

Correspondence to Shivangi Chandrakar .

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Editors and Affiliations

  1. Department of Electrical Engineering, Indian Institute of Technology Jammu, Jammu, India

    Ambika Prasad Shah

  2. Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, India

    Sudeb Dasgupta

  3. Department of Electronics Engineering, Sardar Vallabhbhai National Institute of Technology Surat, Surat, India

    Anand Darji

  4. Department of Computer Science and Engineering, Indian Institute of Technology Tirupati, Tirupati, India

    Jaynarayan Tudu

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Chandrakar, S., Das, K.K., Gupta, D., Majumder, M.K. (2022). Signal Integrity and Power Loss Analysis for Different Bump Structures in Cylindrical TSV. In: Shah, A.P., Dasgupta, S., Darji, A., Tudu, J. (eds) VLSI Design and Test. VDAT 2022. Communications in Computer and Information Science, vol 1687. Springer, Cham. https://doi.org/10.1007/978-3-031-21514-8_30

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  • DOI: https://doi.org/10.1007/978-3-031-21514-8_30

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-031-21513-1

  • Online ISBN: 978-3-031-21514-8

  • eBook Packages: Computer ScienceComputer Science (R0)

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