Abstract
Elliptic curve cryptography (ECC) is one of the most popular asymmetric key cryptography techniques used in secured data communications. The scalar multiplication is the most expensive operation in the ECC. In this paper, we propose a low cost hardware for scalar multiplication in Affine coordinates based ECC. Here, we use a reconfigurable Galois field (GF) arithmetic circuit, which performs various GF arithmetic operations such as addition, multiplication, inverse, and fused multiply add (FMA) using a same set of hardware circuit. Instead of using a number of multipliers and adders in point addition/doubling, we have used only one reconfigurable GF arithmetic circuit. The existing and proposed designs are implemented in 45 nm CMOS technology using Cadence. The synthesis results show that the affine co-ordinate based proposed \(GF(2^{163})\) scalar multiplier achieves \(69\%\) of reduction in the switching power dissipation as compared with the Lopez-Dahab projective co-ordinates based conventional design in 45 nm CMOS technology.
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Acknowledgements
This work is a part of sponsored project (IHUB-NTIHAC/2021/01/1) of C3I Center, IIT Kanpur. Also, this work is fully supported and funded by the same. We thank IHUB-NTIHAC, C3I Center of IIT Kanpur for the given support.
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Inumarty, H., Mohamed Asan Basiri, M. (2022). Low Cost Hardware Design of ECC Scalar Multiplication. In: Shah, A.P., Dasgupta, S., Darji, A., Tudu, J. (eds) VLSI Design and Test. VDAT 2022. Communications in Computer and Information Science, vol 1687. Springer, Cham. https://doi.org/10.1007/978-3-031-21514-8_32
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