Abstract
The state-of-the-art DICE SRAM is immune to Single Node Upset (SNU) in the radiation environment; however, it consumes significant leakage power. The leakage power is reduced in the state-of-the-art Quatro-10T SRAM, but Quatro-10T is not entirely immune to SNU and suffers from it in high radiation environment. In this work, we propose a Radiation Tolerant Quadruple Cross Coupled-14T (RTQCC-14T) SRAM with improved SNU tolerance with the least leakage power among existing techniques. The proposed design also shows better results in other SRAM parameters such as write access time, read access time, read static noise margin, word line write trip voltage and critical charge than most existing techniques. It exhibits better figure of merit among all the state-of-the-art methods. As compared to Quatro-10T, the proposed design has 1.48\(\times \) shorter write access time, 1.42\(\times \) less leakage power, 3.99\(\times \) higher word line write trip voltage, and 1.94\(\times \) higher critical charge respectively @ VDD = 0.9 V at 28 nm CMOS technology.
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Notes
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References
Baumann, R.C.: Soft errors in advanced semiconductor devices-Part I: the three radiation sources. IEEE Trans. Dev. Mater. Reliab. 1(1), 17–22 (2001)
Jahinuzzaman, S.M., Rennie, D.J., Sachdev, M.: A soft error tolerant 10T SRAM bit-cell with differential read capability. IEEE Trans. Nucl. Sci. 56(6), 3768–3773 (2009)
Velazco, R., et al.: SEU-hardened storage cell validation using a pulsed laser. IEEE Trans. Nucl. Sci. 43(6), 2843–2848 (1996)
Calin, T., Nicolaidis, M., Velazco, R.: Upset hardened memory design for submicron CMOS technology. IEEE Trans. Nucl. Sci. 43(6), 2874–2878 (1996)
Amusan, O.A., et al.: Single event upsets in deep-submicrometer technologies due to charge sharing. IEEE Trans. Dev. Mater. Reliab. 8(3), 582–589 (2008)
Qi, C., Xiao, L., Wang, T., Li, J., Li, L.: A highly reliable memory cell design combined with layout-level approach to tolerant single-event upsets. IEEE Trans. Dev. Mater. Reliab. 16(3), 388–395 (2016)
Guo, J., Xiao, L., Mao, Z.: Novel low-power and highly reliable radiation hardened memory cell for 65 nm CMOS technology. IEEE Trans. Circuits Syst. I Regul. Pap. 61(7), 1994–2001 (2014)
Jung, I.-S., Kim, Y.-B., Lombardi, F.: A novel sort error hardened 10T SRAM cells for low voltage operation. In: 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 714–717. IEEE (2012)
Peng, C., et al.: Radiation-hardened 14T SRAM bitcell with speed and power optimized for space application. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 27(2), 407–415 (2018)
Kim, J.S., Chang, I.J., et al.: We-Quatro: radiation-hardened SRAM cell with parametric process variation tolerance. IEEE Trans. Nucl. Sci. 64(9), 2489–2496 (2017)
Chen, J., Chen, S., Liang, B., Liu, B.: Simulation study of the layout technique for P-hit single-event transient mitigation via the source isolation. IEEE Trans. Dev. Mater. Reliab. 12(2), 501–509 (2012)
Li, H., Xiao, L., Qi, C., Li, J.: Design of high-reliability memory cell to mitigate single event multiple node upsets. IEEE Trans. Circuits Syst. I Regul. Pap. 68(10), 4170–4181 (2021)
Han, Y., et al.: Radiation hardened 12T SRAM with crossbar-based peripheral circuit in 28 nm CMOS technology. IEEE Trans. Circuits Syst. I Regul. Pap. 68(7), 2962–2975 (2021)
Pal, S., Mohapatra, S., Ki, W.-H., Islam, A.: Design of soft-error-aware SRAM with multi-node upset recovery for aerospace applications. IEEE Trans. Circuits Syst. I Regul. Pap. 68(6), 2470–2480 (2021)
Prasad, G., Mandi, B.C., Ali, M.: Power optimized SRAM cell with high radiation hardened for aerospace applications. Microelectron. J. 103, 104843 (2020)
Jiang, J., Yiran, X., Zhu, W., Xiao, J., Zou, S.: Quadruple cross-coupled latch-based 10T and 12T SRAM bit-cell designs for highly reliable terrestrial applications. IEEE Trans. Circuits Syst. I Regul. Pap. 66(3), 967–977 (2018)
Acknowledgements
This work is supported through grants received from Science and Engineering Research Board (SERB), Government of India, under CRG/2018/005013, MTR/2019/001605, and SPR/2020/000450.
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Bharti, P.K., Mekie, J. (2022). RTQCC-14T: Radiation Tolerant Quadruple Cross Coupled Robust SRAM Design for Radiation Prone Environments. In: Shah, A.P., Dasgupta, S., Darji, A., Tudu, J. (eds) VLSI Design and Test. VDAT 2022. Communications in Computer and Information Science, vol 1687. Springer, Cham. https://doi.org/10.1007/978-3-031-21514-8_40
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