Abstract
Convolution image filtering technique has been extensively used in image processing applications for sharpening the image, detecting the edges, blurring the image, noise removal etc. Optimization of the convolution algorithm for execution speed has become crucial as the size of the image increases. Loop unrolling is an optimization technique that is adopted for reducing the execution time of the algorithm by reducing the overheads caused by the loops in the algorithm implementation. RISC-V ISA based processing elements being open source are widely used in academia and industry. Hence, in this paper, we have attempted to implement convolution algorithm sequentially and with loop unrolling technique on a custom-developed RISC-V soft core processor. Further, to enhance the speed of operation, a multiprocessor framework has also been developed with Network-on-Chip based inter-core communication platform. The implemented algorithms are tested with RARS tool at assembly level and with Vivado tool at the architectural level. The architecture is also synthesized and implemented on Kintex FPGA evaluation platform.
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Aparna Nair, M.K., Gautam, V.V., Revinipati, A., Soumya, J. (2022). Implementation and Analysis of Convolution Image Filtering with RISC-V Based Architecture. In: Shah, A.P., Dasgupta, S., Darji, A., Tudu, J. (eds) VLSI Design and Test. VDAT 2022. Communications in Computer and Information Science, vol 1687. Springer, Cham. https://doi.org/10.1007/978-3-031-21514-8_42
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