Abstract
This paper describes design and development of OBC-2.3 ASIC based Transmit/Receive controller (TRC) Hardware. This digital hardware is used to control T/R Modules (TRM) of Phased Array Antenna for electronic beam steering in RISAT-1A Synthetic Aperture RADAR. TRC is mainly responsible for Phase computation, Temperature compensation, Temperature data linearization, Beam data loading on transmit /receive event at PRF rate, Tele command etc. The beam information is transmitted by payload controller (PLC) to TRC through Tile Control Unit (TCU) using serial interface. Radiation Hardened Indigenous On Board Controller (OBC-2.3) Application Specific Integrated Circuit (ASIC) is the brain of TRC. The mixed signal OBC-2.3 ASIC is based on 8-bit micro-controller soft IP core. It has inbuilt 32-bit IEEE 754 compliant Floating Point Co-processor (FPC), UART, Event Programmable Serial/Parallel Interface (EPSPI), Transmit/Receive module switch control (TRMSW), RS422 and RS485, ADC etc. modules which are required to control T/R modules and its associated circuitry for different imaging operations. TRC operates at 6 MHz clock and consume less than 1W power. It has been characterized for −15 °C to +75 °C operating environment. This paper also includes the development of Bed of nails test fixture for automatic testing and verification of TRC hardware.
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References
Waldron, T.P., Chin, S.K., Naster, R.J.: Distributed beam steering control of phased array radars. Microwave J., 133–146 (September 1996)
Patel, H., Raman, B.S., Desai, N.M.: Floating point coprocessor for distributed array controller. In: IEEE International Conference on Advances in Computing, Communications and Informatics (ICACCI-2014), New Delhi
Karlstrom, P., Ehliar, A., Liu, D.: High-performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4. IET Comput. Tech. 2(4), 305–313 (2008)
Patel, H., Trivedi, S.M., Neelkanthan, R., Gujraty, V.R.: A robust UART architecture based on recursive running sum filter for better noise performance. In: IEEE International Conference on VLSI design – 2007, Bangalore
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Kumar, R., Singh, A.K., Patel, C., Vinay Kumar, S., Patel, H.N., Saravana Kumar, B. (2022). Development of Distributed Controller for Electronic Beam Steering Using Indigenous Rad-Hard ASIC. In: Shah, A.P., Dasgupta, S., Darji, A., Tudu, J. (eds) VLSI Design and Test. VDAT 2022. Communications in Computer and Information Science, vol 1687. Springer, Cham. https://doi.org/10.1007/978-3-031-21514-8_43
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DOI: https://doi.org/10.1007/978-3-031-21514-8_43
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