Unveiling the Impact of Interface Traps Induced on Negative Capacitance Nanosheet FET: A Reliability Perspective

Abstract

Reliability and yield are major concerns of nano-scaled devices. Bias temperature instability (BTI) has always been one of the major reliability issue for the semiconductor transistors. BTI induced interface traps play a vital role in defining important figures of merits such as threshold voltage (V$_{TH}$), ON current, and $I_{ON}/I_{OFF}$ in terms of the reliability of the transistor, especially in p-type devices. In this paper, for the first time, we investigate the impact of the Si-SiO$_{2}$ interface traps (N$_{it}$) on the performance of the p-type Negative Capacitance Nanosheet (NC-NS) FET. Using well-calibrated TCAD models our results demonstrate that: 1) the end of life (EOL) concentration (i.e., shift of threshold voltage ($\Delta V_{TH}= 50$ mV) in threshold voltage degradation is improved in NC NSFET as compared to baseline NSFET; 2) the smaller degradation in $I_{ON}/I_{OFF}$ and subthreshold slope (SS) is achieved in NC-NSFET. We investigate and evaluate the performance metrics of NC-NS FET in comparison to the baseline NSFET. Our result reveals that NC-NSFET exhibit 2.5 times less degradation in V$_{TH}$, and 11.76x less degradation in $I_{ON}/I_{OFF}$ ratio.