Abstract
The increasing amount of logic resources in FPGA architectures has enabled the realization of larger and more complex designs. Today, most of the large-scale designs rely heavily on off-the-shelf Intellectual Property Cores (IP Cores) to ease their development. This dependency raises an important issue: the unlicensed use of IP Cores. In this paper, we utilize LUT contents, which represent the functionality of an IP Core, as a signature to determine if a core might be part of an accused design. For this, we present a technique to reconstruct the contained LUT contents from modern FPGA configurations which not only contain 6-input one-output LUTs but also 5-input two-output LUTs. By making use of LUT decomposition together with a fast Boolean matching algorithm, we consolidate the work for commercial architectures. The proposed method is evaluated using 8 IP Cores to find in 4 different designs using two different architectures. Our findings show a \(100\%\) identification rate with no false-positives or false-negatives for all experiments carried out. Especially the presence of larger cores can be established with a difference of at least \(10\%\) between true and false positives.
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Notes
- 1.
An example of such a variation is the change of bus-width or address space of peripheral IP Cores.
- 2.
We denote \(\left| s\right| \) as the amount of elements within a set s.
- 3.
\(\varXi _{t,d}\) is true if the template tof a core is present in the design d.
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This work has been funded by Thuringian Ministry for Economics, Science and Digital Society, under grant 2021FGI0008. We are indebted to their support.
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Asghar, A., Robillard, A.K., Tuzov, I., Becher, A., Ziener, D. (2022). Using Look Up Table Content as Signatures to Identify IP Cores in Modern FPGAs. In: Schulz, M., Trinitis, C., Papadopoulou, N., Pionteck, T. (eds) Architecture of Computing Systems. ARCS 2022. Lecture Notes in Computer Science, vol 13642. Springer, Cham. https://doi.org/10.1007/978-3-031-21867-5_9
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