Abstract
With the rapid development of heterogeneous multi-core processors, a new High Performance Computing (HPC) system architecture combining the heterogeneous multi-core architecture and NUMA architecture will emerge in the future. However, existing task mapping methods are ineffective on such systems because they do not simultaneously consider multiple performance factors caused by the heterogeneity in memory access and core performance. In a parallel application, one factor can affect performance more than another depending on the communication and computation load imbalances among parallel tasks. In this case, a task mapping method must prioritize one factor over another when calculating the mapping. To solve this problem, this paper proposes a new mapping method with two task mapping priority options: the memory-aware priority option (MPO) and the heterogeneity-aware priority option (HPO). A priority option switching mechanism (POSM) selects the appropriate priority option for the combination of a system and an application by analyzing their characteristics. Compared with other methods that do not switch mapping priorities, the proposed method achieves overall performance improvement when dealing with a set of applications with different characteristics.
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References
Agung, M., Amrizal, M.A., Egawa, R., Takizawa, H.: DeLoc: a locality and memory-congestion-aware task mapping method for modern NUMA systems. IEEE Access 8, 6937–6953 (2020)
Bailey, D., Harris, T., Saphir, W., Van Der Wijngaart, R., Woo, A., Yarrow, M.: The NAS parallel benchmarks 2.0. Technical report, Technical Report NAS-95-020, NASA Ames Research Center (1995)
Bienia, C., Kumar, S., Singh, J.P., Li, K.: The parsec benchmark suite: characterization and architectural implications. In: Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, pp. 72–81 (2008)
Carlson, T.E., Heirman, W., Eeckhout, L.: Sniper: exploring the level of abstraction for scalable and accurate parallel multi-core simulation. In: Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis, pp. 1–12 (2011)
Che, S., et al.: Rodinia: a benchmark suite for heterogeneous computing. In: 2009 IEEE International Symposium on Workload Characterization (IISWC), pp. 44–54. IEEE (2009)
Chen, J., Nayyar, N., John, L.K.: Mapping of applications to heterogeneous multi-cores based on micro-architecture independent characteristics. In: Third Workshop on Unique Chips and Systems, ISPASS2007 (2017)
Diener, M., Cruz, E.H.M., Alves, M.A.Z., Alhakeem, M.S., Navaux, P.O.A., Heiß, H.-U.: Locality and balance for communication-aware thread mapping in multicore systems. In: Träff, J.L., Hunold, S., Versaci, F. (eds.) Euro-Par 2015. LNCS, vol. 9233, pp. 196–208. Springer, Heidelberg (2015). https://doi.org/10.1007/978-3-662-48096-0_16
Jeannot, E., Mercier, G., Tessier, F.: Process placement in multicore clusters: algorithmic issues and practical techniques. IEEE Trans. Parallel Distrib. Syst. 25(4), 993–1002 (2013)
Mittal, S.: A survey of techniques for architecting and managing asymmetric multicore processors. ACM Comput. Surv. (CSUR) 48(3), 1–38 (2016)
Saez, J.C., Castro, F., Prieto-Matias, M.: Enabling performance portability of data-parallel OpenMP applications on asymmetric multicore processors. In: 49th International Conference on Parallel Processing-ICPP, pp. 1–11 (2020)
Woo, S.C., Ohara, M., Torrie, E., Singh, J.P., Gupta, A.: The splash-2 programs: characterization and methodological considerations. ACM SIGARCH Comput. Architect. News 23(2), 24–36 (1995)
Yu, T., et al.: Collaborative heterogeneity-aware OS scheduler for asymmetric multicore processors. IEEE Trans. Parallel Distrib. Syst. 32(5), 1224–1237 (2020)
Acknowledgements
This work was partially supported by MEXT Next Generation High-Performance Computing Infrastructures and Applications R &D Program “R &D of A Quantum-Annealing-Assisted Next Generation HPC Infrastructure and its Applications,” Grant-in-Aid for Scientific Research(A) #20H00593, Grant-in-Aid for Challenging Research (Exploratory) #22K19764, and JST, the establishment of university fellowships towards the creation of science technology innovation, Grant Number JPMJFS2102.
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Jin, Y., Agung, M., Takahashi, K., Shimomura, Y., Takizawa, H. (2023). Towards Priority-Flexible Task Mapping for Heterogeneous Multi-core NUMA Systems. In: Takizawa, H., Shen, H., Hanawa, T., Hyuk Park, J., Tian, H., Egawa, R. (eds) Parallel and Distributed Computing, Applications and Technologies. PDCAT 2022. Lecture Notes in Computer Science, vol 13798. Springer, Cham. https://doi.org/10.1007/978-3-031-29927-8_1
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