Abstract
Filters with a finite impulse response are important blocks in signal reception and processing applications. The relatively high complexity of FIR filters implementation in FPGA is due to the high number of multiply and accumulate (MAC) operations, and, consequently, the high number of on-chip multipliers used. Distributed arithmetic (DA) is an alternative approach of replacing on-chip multipliers with shift registers, look-up-tables (LUT) and adders. However, in DA approach the storage size grows rapidly as the filter order increases. Moreover the supported sampling frequency is inversely proportional to the input samples bit width in DA. This paper proposes a modified DA hardware architecture with reduced memory consumption and doubled maximum supported sampling frequency. The resources consumption of proposed architecture after its implementation in FPGA is lower compared to existing DA implementations.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Rojo-Álvarez, J.L., Martínez-Ramón, M., Muñoz-Marí, J., Camps-Valls, G.: Introduction to Digital Signal Processing (2018)
Smith, S.W., et al.: The scientist and engineer’s guide to digital signal processing (1997)
Hawkes, G.C.: Digital signal processing: designing for optimal results. high-performance DSP using virtex-4 FPGAs by xilinx, Edition 1.0 (2005)
Peled, A., Liu, B.: A new hardware realization of digital filters. IEEE Trans. Acoust. Speech Signal Process. 22(6), 456–462 (1974)
Levilion, M.E., Rizo, V., Croisier, A., Esteban, D.J.: Digital filter for PCM encoded signals. U.S. Patent 00208345A (1973)
Allred, D.J., Yoo, H., Krishnan, V., Huang, W., Anderson, D.V.: LMS adaptive filters using distributed arithmetic for high throughput. IEEE Trans. Circ. Syst. I Regular Pap. 52(7), 1327–1337 (2005)
Guo, R., DeBrunner, L.S.: A novel adaptive filter implementation scheme using distributed arithmetic. In: 2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR), pp. 160–164 (2011)
Rawski, M., Wojtynnski, M., Wojciechowski, T., Majkowski, P.: Distributed arithmetic based implementation of Fourier transform targeted at FPGA architectures. In: 2007 14th International Conference on Mixed Design of Integrated Circuits and Systems, pp. 152–156 (2007)
Hong, B., Yin, H., Wang, X., Xiao, Y.: Implementation of FIR filter on FPGA using DAOBC algorithm. In: The 2nd International Conference on Information Science and Engineering, pp. 3761–3764 (2010)
Schroder, H.: High word-rate digital filters with programmable table look-up. IEEE Trans. Circ. Syst. 24(5), 277–279 (1977)
NagaJyothi, G., SriDevi, S.: Distributed arithmetic architectures for FIR filters-a comparative review. In: 2017 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET), pp. 2684–2690 (2017)
Author information
Authors and Affiliations
Corresponding authors
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2023 The Author(s), under exclusive license to Springer Nature Switzerland AG
About this paper
Cite this paper
Kozorez, K., Rashich, A. (2023). Reduced Complexity Distributed Arithmetic Architecture for FIR Filters. In: Koucheryavy, Y., Aziz, A. (eds) Internet of Things, Smart Spaces, and Next Generation Networks and Systems. NEW2AN 2022. Lecture Notes in Computer Science, vol 13772. Springer, Cham. https://doi.org/10.1007/978-3-031-30258-9_49
Download citation
DOI: https://doi.org/10.1007/978-3-031-30258-9_49
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-031-30257-2
Online ISBN: 978-3-031-30258-9
eBook Packages: Computer ScienceComputer Science (R0)