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A Novel Fast Recovery Method for HT Tamper in Embedded Processor

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Blockchain Technology and Emerging Technologies (BlockTEA 2022)

Abstract

Nowadays, embedded processors face various hardware security issues such as hardware trojans (HT) and code tamper attacks. In this paper, a novel cycle-level recovery method for HT tamper in embedded processor is proposed, which consists two units, a General-Purpose Register (GPRs) backup unit and a PC rollback unit. The former one is designed to replace original register files with backup function extra. And the latter one is composed for rollback operations based on the exact PC address corresponding to the wrong instruction. If a HT tamper is detected, the backup unit works in conjunction with PC rollback unit allowing the processor to resume the instruction execution. The proposed method has been implanted into a RISC-V core of PULpino, and the experimental results show that the processor can restore from fault state caused by inserted HT in real time with the latency of 7 clock cycles, including 2 clock cycles for detection.

Supported by University of Electronic Science and Technology of China.

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References

  1. Bhunia, S., Hsiao, M.-S., Banga, M., Narasimhan, S.: Hardware trojan attacks: threat analysis and countermeasures. In: Proceedings of the IEEE, pp. 1229–1247. IEEE (2014)

    Google Scholar 

  2. Kuo, M.-H., Hu, C.-M., Lee, K.-J.: Time-related hardware trojan attacks on processor cores. In: IEEE International Test Conference in Asia (ITC-Asia), pp. 43–48. IEEE, Tokyo (2019)

    Google Scholar 

  3. Okane, P., Sezer, S., McLaughlin, K., Im, E.: Malware detection: program run length against detection rate. IET Softw. 8(1), 42–51 (2014)

    Article  Google Scholar 

  4. Duflot, L.: CPU bugs, CPU backdoors and consequences on security. J. Comput. Virol. 5(2), 91–104 (2008)

    Article  Google Scholar 

  5. Zhou, L., Makris, Y.: Hardware-based on-line intrusion detection via system call routine fingerprinting. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1546–1551. IEEE, Lausanne (2017)

    Google Scholar 

  6. Liu, L., et al.: Jintide®: a hardware security enhanced server CPU with xeon® cores under runtime surveillance by an in-package dynamicall reconfigurable processor. In: 2019 IEEE Hot Chips 31 Symposium (HCS), pp. 1–25. IEEE, Cupertino (2019)

    Google Scholar 

  7. Hoque, T., Wang, X., Basak, A., Karam, R., Bhunia, S.: Hardware Trojan attacks in embedded memory. In: 2018 IEEE 36th VLSI Test Symposium (VTS), pp. 1–6. IEEE, San Francisco (2018)

    Google Scholar 

  8. Wang, X., Mal-Sarkar, T., Krishna, A., Narasimhan, S., Bhunia, S.: Software exploitable hardware Trojans in embedded processor. In: 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp. 55–58. IEEE, Austin (2012)

    Google Scholar 

  9. Zhao, Y., Wang, X., Jiang, Y., Mei, Y., Singh, A.-K., Mak, T.: On a new hardware Trojan attack on power budgeting of many core systems. In: 31st IEEE International System-on-Chip Conference (SOCC), pp. 1–6. IEEE, Arlington, VA, USA (2018)

    Google Scholar 

  10. Zhou, J., Li, M., Guo, P., Liu, W.: Mitigation of tampering attacks for MR-based thermal sensing in optical NoCs. In: 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 554–559. IEEE, Limassol, Cyprus (2020)

    Google Scholar 

  11. Zaraee, N., Zhou, B., Vigil, K., Shahjamali, M., Joshi, A., Selim, Ü.M.: Gate-level validation of integrated circuits with structured-illumination read-out of embedded optical signatures. IEEE Access 8, 70900–70912 (2020)

    Article  Google Scholar 

  12. Chhabra, S., Lata, K.: Key-based Obfuscation using HT-like Trigger Circuit for 128-bit AES Hardware IP Core. In: 34th International System-on-Chip Conference (SOCC), pp. 164–169. IEEE, Las Vegas, NV, USA (2021)

    Google Scholar 

  13. Ma, H., et al.: On-chip trust evaluation utilizing TDC-based parameter-adjustable security primitive. IEEE Trans. TCAD 40(10), 1985–1994 (2021)

    Google Scholar 

  14. Lin D, Wu C.: Real-time active tampering detection of surveillance camera and implementation on digital signal processor. In: 2012 Eighth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, pp. 383–386. IEEE, Piraeus-Athens, Greece (2012)

    Google Scholar 

  15. Baba Y, Homma N, Miyamoto A, Aoki T.: Design of tamper-resistant registers for multiple-valued cryptographic processors. In: 40th IEEE International Symposium on Multiple-Valued Logic, pp. 67–72. IEEE, Barcelona, Spain (2010)

    Google Scholar 

  16. Yang, J., Zhang, Y., Gao, L.: Fast secure processor for inhibiting software piracy and tampering. In: 36th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 351–360. IEEE, San Diego, CA, USA (2003)

    Google Scholar 

  17. Bashiri, M., Miremadi, S.-G., Fazeli, M.: A Checkpointing technique for rollback error recovery in embedded systems. In: 2006 International Conference on Microelectronics, pp. 174–177. IEEE, Dhahran, Saudi Arabia (2006)

    Google Scholar 

  18. Xu, M., Zhao, H., Li, J., Zhang, H.: Steady rollback and recovery policy based on integrity measurement. In: 2010 IEEE International Conference on Intelligent Computing and Intelligent Systems, pp. 834–836. IEEE, Xiamen (2010)

    Google Scholar 

  19. Chen, C.-H., Ting, Y, Heh, J.-S.: Low overhead incremental checkpointing and rollback recovery scheme on windows operating system. In: Third International Conference on Knowledge Discovery and Data Mining, pp. 268–271. IEEE, Phuket, Thailand (2010)

    Google Scholar 

  20. Tamir, Y., Tremblay, M.: High-performance fault-tolerant VLSI systems using micro rollback. IEEE Trans. Comput. 39(4), 548–554 (1990)

    Article  Google Scholar 

  21. Slegel, T.-J., et al.: IBM’s S/390 G5 microprocessor design. IEEE Micro 19(2), 12–23 (1999)

    Article  Google Scholar 

  22. Sorin, D., Martin, M., Hill, M., Wood, D.: SafetyNet: improving the availability of shared memory multiprocessors with global checkpoint/recovery. In: 29th Annual International Symposium on Computer Architecture, pp. 123–134. IEEE, Anchorage, AK, USA (2002)

    Google Scholar 

  23. Salehi, M., Khavari, T.-M., Rehman, S., Shafique, M., Ejlali, A., Henkel, J.: Two-state checkpointing for energy-efficient fault tolerance in hard real-time systems. IEEE Trans. VLSI 24(7), 2426–2437 (2016)

    Article  Google Scholar 

  24. Li, T., Ambrose, J., Parameswaran, S..: RECORD: reducing register traffic for checkpointing in embedded processors. In: 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 582–587. IEEE, Dresden, Germany (2016)

    Google Scholar 

  25. Do, X., Ha, V., Tran, V., Renault, É.: The technique of locking memory on Linux operating system - application in checkpointing. In: 6th NAFOSTED Conference on Information and Computer Science (NICS), pp. 178–183. IEEE, Hanoi, Vietnam (2019)

    Google Scholar 

  26. Wang, X., Zhao, Z., Xu, D., Zhang, Z., Hao, Q., Liu, M.: An M-cache-based security monitoring and fault recovery architecture for embedded processor. IEEE Trans. VLSI 28(11), 2314–2327 (2020)

    Article  Google Scholar 

  27. Chaudhari, A., Park, J., Abraham, J.: A framework for low overhead hardware based runtime control flow error detection and recovery. In: 31st VLSI Test Symposium (VTS), pp. 1–6. IEEE, Berkeley, CA, USA (2013)

    Google Scholar 

  28. Huu, N., Robisson, B., Agoyan, M., Drach, N.: Low-cost recovery for the code integrity protection in secure embedded processors. In: 2011 IEEE International Symposium on Hardware-Oriented Security and Trust, pp. 99–104. IEEE, San Diego, CA, USA (2011)

    Google Scholar 

  29. Gizopoulos, D., et al.: Architectures for online error detection and recovery in multicore processors. In: 2011 Design, Automation & Test in Europe, pp. 1–6. IEEE, Grenoble, France (2011)

    Google Scholar 

  30. Kundu, K., Khan, O.: Efficient error-detection and recovery mechanisms for reliability and resiliency of multicores. In: 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), pp. 12–13. IEEE, Kolkata, India (2016)

    Google Scholar 

  31. Zhou, W.-T., Li, L., Yuan, S.-W.: China Patent, vol. 202210262087, pp. 4 (2022)

    Google Scholar 

  32. PULpino Datasheet. https://pulp-platform.org/docs/pulpino_datasheet.pdf

  33. PULpino Project. https://github.com/pulpplatform/pulpino

  34. Yuan, S.-W., Li, L., He, Y.-H., Zhou, W.-T., Li, J.: Real-time detection of hardware trojan attacks on general-Purpose Registers in a RISC-V processor. IEICE Electron. Express 18(10), 1–3 (2021)

    Article  Google Scholar 

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Acknowledgments

This work is partly supported by Sichuan Science and Technology Program under Grant 2021YJ0082. And the authors would like to thank IC Team for providing advice and discussion.

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Correspondence to Wanting Zhou .

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Zhou, W., Yuan, S., Li, L., Yeh, KH. (2023). A Novel Fast Recovery Method for HT Tamper in Embedded Processor. In: Meng, W., Li, W. (eds) Blockchain Technology and Emerging Technologies. BlockTEA 2022. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 498. Springer, Cham. https://doi.org/10.1007/978-3-031-31420-9_8

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  • DOI: https://doi.org/10.1007/978-3-031-31420-9_8

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