Abstract
Recent research in both academia and industry has successfully used deductive verification to design hardware and prove its correctness. While tools and languages to write formally proved hardware have been proposed, applications and use cases are often overlooked. In this work, we focus on Dynamic Random Access Memories (DRAM) controllers and the DRAM itself – which has its expected temporal and functional behaviours described in the standards written by the Joint Electron Device Engineering Council (JEDEC). Concretely, we associate an existing Coq DRAM controller framework – which can be used to write DRAM scheduling algorithms that comply with a variety of correctness criteria – to a back-end system that generates proved logically equivalent hardware. This makes it possible to simultaneously enjoy the trustworthiness provided by the Coq framework and use the generated synthesizable hardware in real systems. We validate the approach by using the generated code as a plug-in replacement in an existing DDR4 controller implementation, which includes a host interface (AXI), a physical layer (PHY) from Xilinx, and a model of a memory part Micron MT40A1G8WE-075E:D. We simulate and synthesise the full system.
This research was supported by Labex DigiCosme (project ANR11L- ABEX0045DIGICOSME) operated by ANR as part of the program “Investissement d’Avenir” Idex ParisSaclay (ANR11IDEX000302).
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Notes
- 1.
- 2.
CAS commands tell the memory to start the data transfer – its issue date is considered to be the completion date of the corresponding request.
- 3.
- 4.
In the listing, the notation
stands for circuit composition. - 5.
Initial register values are omitted from the figure.
- 6.
PREA commands are PRE commands sent to every bank at once.
- 7.
- 8.
Inasmuch as the PHY runs at the system clock frequency (1/4 of the DRAM clock frequency), it expects four command/address per system clock and issues them serially on consecutive DRAM clock cycles on the DRAM bus. This means that the PHY interface provides four command slots: 0,1,2, and 3, which it accepts each system clock. To cope with the different clock domains, we insert CavaDRAM commands always in the first slot. The proofs in CoqDRAM do not lose validity, as lower-bounds still hold. The only proofs that need adapting are REF related proofs, as they are upper bounds on the spacing between REF commands. We write modified version of such constraints considering the different clock domains.
- 9.
stands for circuit composition.References
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Acknowledgement
We acknowledge and are grateful for the contributions of Sumantha Chaudhuri, who provided help setting up the simulation environment; Chirag Sudarshan, who made himself available for discussing the implementation of DDR4cntrl; and Lirida Naviner for insightful discussions. This work is supported by the European Union’s Horizon 2020 research and innovation program under grant agreement No. 101070627 (REWIRE).
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Malaquias, F.L., Asavoae, M., Brandner, F. (2023). From the Standards to Silicon: Formally Proved Memory Controllers. In: Rozier, K.Y., Chaudhuri, S. (eds) NASA Formal Methods. NFM 2023. Lecture Notes in Computer Science, vol 13903. Springer, Cham. https://doi.org/10.1007/978-3-031-33170-1_18
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