Abstract
This paper proposes a blind oversampling data recovery algorithm LUT-DRC (Data Recovery Algorithm Based on Look-Up Table) for 100Base-FX. The LUT-DRC can recover all data in an Ethernet packet of any length, even a clock jitter of \(8\,ns\,\pm \,0.03125\,ns\) at the transmitter. The LUT-DRC core consists of only 470 LUT6, 1 block RAM, and 1 PLL (Phase-Locked Loop, PLL) and has an estimated power consumption of 10 mW at 125 Mbps. LUT-DRC was implemented on a PANGO PGL25 FPGA device and tested using a NuStreams-700 network tester. No CRC (Cyclic Redundancy Check, CRC) errors were found during data transfer testing using \(2.5 * 10^8\) Ethernet packets. The characteristics of LUT-DRC and its performance make it suitable for any FPGA to implement 100BASE-FX communication without a 100BASE-FX PHY (Physical Layer Transceiver, PHY) chip.
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Luo, G., Wang, Q., Liu, Y., Zhang, Y., Sun, H., Zhou, Q. (2023). Implementation of an All-Digital DRC for 100BASE-FX. In: Yu, S., Gu, B., Qu, Y., Wang, X. (eds) Tools for Design, Implementation and Verification of Emerging Information Technologies. TridentCom 2022. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 489. Springer, Cham. https://doi.org/10.1007/978-3-031-33458-0_5
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