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Verifying Chips Design at RTL Level

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Theoretical Aspects of Software Engineering (TASE 2023)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 13931))

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Abstract

With the increasing complexity of chips design, the design errors or defects will inevitably increase. It is difficult to detect corresponding design logic problems with some conventional detection methods, such as testing and simulation. Further, the cost of such detection processes is also expensive. In contrast, formal verification methods based on mathematical logic reasoning about formal description capabilities can strictly prove whether a system meets the expected demand properties, so that it can effectively find out hidden defects or errors in chips design. Model checking is a widely used formal method for verifying chips design. However, model checking suffers from so called state space explosion problem. Although traditional model checking method alleviates the problem of state space explosion to a certain extent, there is still the problem of slow solution efficiency for large-scale chips design. Bounded model checking detects the limited path of a model to quickly determine the hidden problems of chips design, which can effectively alleviate the problem of system state space explosion. However, most of the logic languages such as LTL or CTL used in describing the desired properties cannot describe full regular properties of chips design. Further, the most of verification processes are based on symbolic model checking which is ineffective to detect design bugs in practice. Therefore, this paper focuses on the use of PPTL in bounded model checking to describe the properties to be verified and makes full use of SAT solvers to convert bounded model checking problems into SAT instances so that the scope and scale of verification of chips design can be reinforced and the efficiency of the verification processes can be also improved.

This research is supported by National Natural Science Foundation of China under Grant Nos. 62272359 and 62172322; Natural Science Basic Research Program of Shaanxi Province under Grant Nos. 2023JC-XJ-13 and 2022JM-367.

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Authors and Affiliations

  1. Institute of Computing Theory and Technology, and ISN Laboratory, Xidian University, Xi’an, 710071, China

    Wu Wang, Nan Zhang, Cong Tian, Zhenhua Duan, Zhijie Xu & Chaofeng Yu

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  1. Wu Wang
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Correspondence to Zhenhua Duan .

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Editors and Affiliations

  1. University of Bristol, Bristol, UK

    Cristina David

  2. Peking University, Beijing, China

    Meng Sun

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Wang, W., Zhang, N., Tian, C., Duan, Z., Xu, Z., Yu, C. (2023). Verifying Chips Design at RTL Level. In: David, C., Sun, M. (eds) Theoretical Aspects of Software Engineering. TASE 2023. Lecture Notes in Computer Science, vol 13931. Springer, Cham. https://doi.org/10.1007/978-3-031-35257-7_9

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  • DOI: https://doi.org/10.1007/978-3-031-35257-7_9

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