Abstract
3D integrated circuit was presented as a new solution to enhance the efficiency and expand the capabilities of modern integrated circuit as well. Studies have shown that in comparison with 2D NoCs, the proposed 3D NoC offers a lower power consumption, shorter delay and high performance due to the reduction of the connection length in 3D NoCs. In this article, we present a routing algorithm for heterogeneous 3D NoC which distributes the chip traffic in the whole network based on the global congestion information. This is achieved by finding the least congested minimal path between the communicating nodes. For vertical connections, we consider the Through-Silicon-Vias (TSV) and to avoid deadlock, we use two virtual channels. The results show that the proposed mechanism is superior in comparison with the Elevator-First algorithm in the similar working condition.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Xu, T.C., Schley, G., Liljeberg, P., Radetzki, M., Plosila, J., Tenhunen, H.: Optimal placement of vertical connections in 3D network-on-chip. J. Syst. Architect. 59, 441–454 (2013)
Tanaka, N., et al.: Through-silicon via interconnection for 3D integration using room-temperature bonding. IEEE Trans. Adv. Packag. 32, 746–753 (2009)
Pavlidis, V.F., Friedman, E.G.: Three-Dimensional Integrated Circuit Design. Morgan Kaufmann, Burlington, MA (2009)
Rahmani, A.-M., Vaddina, K.R., Liljeberg, P., Plosila, J., Tenhunen, H.: Power and area optimization of 3D networks-on-chip using smart and efficient vertical channels. Integrated circuit and system design. In: Power and Timing Modeling, Optimization, and Simulation, pp. 278–287. Springer, Heidelberg (2011). https://doi.org/10.1007/978-3-642-11802-9
Liljeberg, P., Plosila, J., Tenhunen, H., Feero, B.S., Pande, P.P.: Networks-on-chip in a three-dimensional environment: a performance evaluation, IEEE Transactions on Computers, 2009, Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, pp. 278–287 (2011)
Pavlidis, V., Friedman, E.: 3-D topologies for networks-on-chip. In: 2006 IEEE International SOC Conference (2006)
Velenis, D., Stucchi, M., Marinissen, E.J., Swinnen, B., Beyne, E.: Impact of 3D design choices on manufacturing cost. In: 2009 IEEE International Conference on 3D System Integration (2009)
Shang, L., Peh, L., Kumar, A., Jha, N.K.: Thermal modeling, characterization and management of on-chip networks. In: 37th International Symposium on Microarchitecture (MICRO-37'04)
Zhu, C., Gu, Z., Shang, L., Dick, R.P., Joseph, R.: Three-dimensional chip-multiprocessor run-time thermal management. IEEE Trans. Comput.-Aid. Design Integr. Circ. Syst. 27, 1479–1492 (2008)
Ebrahimi, M., Daneshtalab, M.: Learning-based routing algorithms for on-chip networks. In: Palesi, M., Daneshtalab, M. (eds.) Routing Algorithms in Networks-on-Chip. Springer, New York, pp. 105–125 (2014). https://doi.org/10.1007/978-1-4614-8274-1_5
Ramanujam, R.S., Lin, B.: Near-optimal oblivious routing on three-dimensional mesh networks. In: 2008 IEEE International Conference on Computer Design. (2008)
Tyagi, S .: Extended balanced dimension ordered routing algorithm for 3D-networks. In: India International Conference on Parallel processing Workshops, pp. 499–506. Centre for Development of Advance Computing, Noida, (U.P.) (2009)
Zhu, M., Lee, J., Choi, K.: An adaptive routing algorithm for 3D mesh NOC with limited vertical bandwidth. In: 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC). (2012)
Dubois, F., Sheibanyrad, A., Petrot, F., Bahmani, M.: Elevator-first: A deadlock-free distributed routing algorithm for vertically partially connected 3D-nocs. IEEE Trans. Comput. 62, 609–615 (2013)
Dally, S.: Deadlock-free message routing in multiprocessor interconnection networks. IEEE Trans. Comput. C-36, 547–553 (1987)
Rosen, K.H.: Discrete Mathematics and Its Applications. Braille Jymico Inc., Charlesbourg (1993)
Glass, C.J., Ni, L.M.: The turn model for adaptive routing. In: Proceedings the 19th Annual International Symposium on Computer Architecture (1992)
Kim, J., Park, D., Theocharides, T., Vijaykrishnan, N., Das, C.R.: A low latency router supporting adaptivity for on-chip interconnects. In: Proceedings of 42nd Design Automation Conference, 2005 (2005)
Jheng, K.Y., Chao, C.H., Wang, H.Y., Wu, A.Y.: Traffic-thermal mutual-coupling co-simulation platform for three-dimensional network-on-chip. In: Proceedings of 2010 International Symposium on VLSI Design, Automation and Test (2010)
Puttaswamy, K., Loh, G.H.: Thermal herding: Microarchitecture techniques for controlling hotspots in high-performance 3D-integrated processors. In: 2007 IEEE 13th International Symposium on High Performance Computer Architecture (2007)
Link, G.M., Vijaykrishnan, N.: Hotspot prevention through runtime reconfiguration in Network-on-chip. In: Proceedings of the conference on Design, Automation and Test in Europe (2005)
Sun, C., et al.: DSENT - a tool connecting emerging photonics with electronics for opto-electronic networks-on-chip modeling. In: 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip (2012)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2023 The Author(s), under exclusive license to Springer Nature Switzerland AG
About this paper
Cite this paper
Majidzadeh, S. (2023). A Load Balancing Mechanism for 3D Network-on-Chip with Partially Vertically Connected Links. In: Camarinha-Matos, L.M., Ferrada, F. (eds) Technological Innovation for Connected Cyber Physical Spaces. DoCEIS 2023. IFIP Advances in Information and Communication Technology, vol 678. Springer, Cham. https://doi.org/10.1007/978-3-031-36007-7_19
Download citation
DOI: https://doi.org/10.1007/978-3-031-36007-7_19
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-031-36006-0
Online ISBN: 978-3-031-36007-7
eBook Packages: Computer ScienceComputer Science (R0)
