Polynomial Formal Verification of Complex Circuits Using a Hybrid Proof Engine

Abstract

The size and complexity of digital circuits are increasing; thus, they are becoming more and more error-prone. In order to prevent the bugs from escaping to silicon, formal verification is a mandatory and important phase after the design. In particular, Polynomial Formal Verification (PFV) has gotten a lot of attention in recent years, since it makes the verification process scalable and predictable in terms of memory usage and run-time. However, applying PFV is not always easy, especially when it comes to complex circuits.

In this paper, the concept of PFV is reviewed. Then, we introduce a hybrid proof engine to attack the problem of verifying complex modern systems in polynomial space and time. The engine takes advantage of several verification techniques, such as combinational equivalence checking based on bit-level approaches, like SAT and Binary Decision Diagrams (BDDs), as well as word-level verification based on e.g. Symbolic Computer Algebra (SCA) and Word-Level Decision Diagrams (WLDDs). The correctness of each block or system task can be ensured in polynomial time using a specific verification technique from the environment. Thus, we overcome the shortcomings of using only one verification method and pave the way toward polynomial verification of highly complex architectures.