Abstract
The last decade has seen high-performance computing (HPC) systems become denser and denser. Higher node and rack density has led to development of multi-level networks - at socket, node, ‘pod’, rack, and between nodes. As sockets become more complex with integrated or co-packaged heterogeneous architectures, this network complexity is going to increase. In this paper, we extend Structural Simulation Toolkit (SST) to model these multi-level networks designs. We demonstrate this newly introduced capability by modeling a combination of a few different network topologies at different levels of the system and simulating the performance of collectives and some popular HPC communication patterns.
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References
Frontier: ORNL’s exascale supercomputer designed to deliver world-leading performance in 2021. https://www.olcf.ornl.gov/frontier/
Stevens, R., Ramprakash, J., Messina, P., Papka, M., Riley, K.: Aurora: argonne’s next-generation exascale supercomputer. United States (2019)
Choquette, J.: NVIDIA hopper H100 GPU: scaling performance. IEEE Micro (2023). https://doi.org/10.1109/MM.2023.3256796
Smith, A., Norman, J.: AMD Instinct™ MI200 series accelerator and node architectures. In: 2022 IEEE Hot Chips 34 Symposium (HCS). IEEE Computer Society (2022)
https://www.intel.com/content/www/us/en/newsroom/news/intel-technology-roadmaps-milestones.html
Rodrigues, A.F., et al.: The structural simulation toolkit. ACM SIGMETRICS Perform. Eval. Rev. 38(4), 37–42 (2011)
Casanova, H., Legrand, A., Quinson, M.: SimGrid: a generic framework for large-scale distributed experiments. In: Tenth International Conference on Computer Modeling and Simulation (uksim 2008), pp. 126–131. IEEE (2008)
Mubarak, M., et al.: Enabling parallel simulation of large-scale HPC network systems. IEEE Trans. Parallel Distrib. Syst. 28(1), 87–100 (2016)
Musleh, M., et al.: Fabsim-X: a simulation framework for the analysis of large-scale topologies and congestion control protocols in data center networks. In: 2020 28th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS). IEEE(2020)
Riley, G.F., Henderson, T.R.: The ns-3 network simulator. In: Wehrle, K., Günes, M., Gross, J. (eds.) Modeling and Tools for Network Simulation, pp. 15–34. Springer, Heidelberg (2010). https://doi.org/10.1007/978-3-642-12331-3_2
Varga, A., Rudolf, H.: An overview of the OMNeT++ simulation environment. In: 1st International ICST Conference on Simulation Tools and Techniques for Communications, Networks and Systems (2010)
Jiang, N., et al.: A detailed and flexible cycle-accurate network-on-chip simulator. In: 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). IEEE (2013)
Li, S., et al.: DRAMsim3: a cycle-accurate, thermal-capable DRAM simulator. IEEE Comput. Archit. Lett. 19(2), 106–109 (2020)
Stevens, J., et al.: An integrated simulation infrastructure for the entire memory hierarchy: cache, dram, nonvolatile memory, and disk. Intel Technol. J. 17(1), 184–200 (2013)
Leidel, J.D., Yong, C.: HMC-sim-2.0: a simulation platform for exploring custom memory cube operations. In: 2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). IEEE (2016)
Kim, Y., Yang, W., Mutlu, O.: Ramulator: a fast and extensible DRAM simulator. IEEE Comput. Archit. Lett. 15(1), 45–49 (2015)
Bakhoda, A., et al.: Analyzing CUDA workloads using a detailed GPU simulator. In: 2009 IEEE International Symposium on Performance Analysis of Systems and Software. IEEE (2009)
Muñoz-Martínez, F., et al.: STONNE: enabling cycle-level microarchitectural simulation for DNN inference accelerators. In: 2021 IEEE International Symposium on Workload Characterization (IISWC). IEEE (2021)
Acknowledgements
We would like to thank Scott Hemmert from Sandia National Laboratories for answering our questions and helping us understand the SST backend better.
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Chenna, S.P., Kumar, N., Borges, L., Steyer, M., Thierry, P., Garzaran, M. (2023). Enabling Multi-level Network Modeling in Structural Simulation Toolkit for Next-Generation HPC Network Design Space Exploration. In: Bienz, A., Weiland, M., Baboulin, M., Kruse, C. (eds) High Performance Computing. ISC High Performance 2023. Lecture Notes in Computer Science, vol 13999. Springer, Cham. https://doi.org/10.1007/978-3-031-40843-4_27
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DOI: https://doi.org/10.1007/978-3-031-40843-4_27
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