Abstract
The emergence of RISC-V as a reduced instruction set architecture has brought several advantages such as openness, flexibility, scalability, and efficiency compared to other commercial ISAs. It has gained significant popularity, especially in the field of high-performance computing. However, there is a lack of high-performance implementations of numerical algorithms, including the Fast Fourier Transform (FFT) algorithm. To address this issue, the paper focuses on optimizing the butterfly network, butterfly kernel, and single instruction multiple data (SIMD) operations to achieve efficient calculations for FFT with a computation scale of \(2^n\) on a RISC-V architecture CPUs. The experimental results demonstrate a significant improvement in the performance of the FFT algorithm library implemented using the proposed optimizations compared to existing implementations like FFTW on RISC-V CPUs.
X. Zhang—This work is partly supported by Beijing Municipal Science and Technology Program under Grant No. Z211100004421002.
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Zhao, X., Zhang, X., Zhang, Y. (2023). Optimization of the FFT Algorithm on RISC-V CPUs. In: Bienz, A., Weiland, M., Baboulin, M., Kruse, C. (eds) High Performance Computing. ISC High Performance 2023. Lecture Notes in Computer Science, vol 13999. Springer, Cham. https://doi.org/10.1007/978-3-031-40843-4_38
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