Abstract
Many papers proposed the execution of real-time tasks on FPGA hardware. Most of these works do not demonstrate fully working systems and suffer from either unrealistic assumptions about the placement, reconfigurability, and connectivity of hardware tasks to memory and peripherals, or do not come with an efficient schedulability test that guarantees that real-time constraints are met.
In this paper, we present a practical way of executing a set of periodic real-time tasks under static priority assignment on a platform FPGA, comprising a processing system and programmable logic. The platform FPGA is operated under the ReconOS\(^{64}\) architecture and operating system layer which enables practical realization. The hardware tasks follow a 3-phase task model with memory-in, execution, and memory-out phases. All memory phases compete for shared memory, which forms a resource that must be accessed mutually exclusive. While our task and system models are relatively simple as they map each hardware task to a separate region in the programmable logic, they lead to an efficient schedulability test covering memory accesses. We present our task and ReconOS\(^{64}\) system models, describe the runtime scheduler, and derive a corresponding schedulability test.
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Acknowledgments
This work was partially supported by the German Research Foundation (DFG) within the Collaborative Research Centre On-The-Fly Computing (GZ: SFB 901/3) under the project number 160364472.
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Clausing, L., Guettatfi, Z., Kaufmann, P., Lienen, C., Platzner, M. (2023). On Guaranteeing Schedulability of Periodic Real-Time Hardware Tasks Under ReconOS\(^{64}\). In: Palumbo, F., Keramidas, G., Voros, N., Diniz, P.C. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2023. Lecture Notes in Computer Science, vol 14251. Springer, Cham. https://doi.org/10.1007/978-3-031-42921-7_17
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