Abstract
The number of Additions Per Output Sample (APOS) is, currently, a standard way to estimate the computational complexity of Cascaded Integrator-Comb (CIC) decimators. This metric originates from a perspective with a high level of abstraction, where the amount of additions performed by the CIC hardware architecture accounts in general for the switching activity of the system, and therefore represents the power consumption in a direct proportion. In this paper we introduce an approach that leads towards a more appropriate way to estimate the computational complexity of CIC decimators, which considers the width of the internal buses of the architecture. We employ the pruning scheme by Hogenauer, and we provide explicit formulas to find, through a simple procedure, the number of Atomic Additions Per Output Sample (AAPOS), which accounts for the computational complexity on a bit-by-bit (i.e., atomic) basis. Three detailed examples are included to show how the AAPOS provides different results for systems with apparently equal computational complexity when estimated with APOS, leading to a more precise and trustable estimation.
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Romero, D.E.T., Pacheco, J.C.R., Borges, J.A.L., Cruz, H.T. (2023). APOS is Not Enough: Towards a More Appropriate Way to Estimate Computational Complexity in CIC Decimation Architectures. In: Mata-Rivera, M.F., Zagal-Flores, R., Barria-Huidobro, C. (eds) Telematics and Computing. WITCOM 2023. Communications in Computer and Information Science, vol 1906. Springer, Cham. https://doi.org/10.1007/978-3-031-45316-8_2
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DOI: https://doi.org/10.1007/978-3-031-45316-8_2
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